179 lines
3.9 KiB
Python
179 lines
3.9 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.sim.generic import Simulator, PureSimulable, TopLevel
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from migen.sim.icarus import Runner
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from migen.bus.transactions import *
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import sys
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sys.path.append("../")
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from migScope import trigger, recorder
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from migScope.tools.truthtable import *
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from migScope.tools.vcd import *
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TRIGGER_ADDR = 0x0000
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RECORDER_ADDR = 0x0200
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rec_done = False
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dat_rdy = False
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dat_vcd = []
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def term_prog(off, dat):
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for i in range(4):
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yield TWrite(off+3-i, (dat>>(8*i))&0xFF)
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def sum_prog(off, addr, dat):
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we = 2
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yield TWrite(off+3, addr%0xFF)
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yield TWrite(off+2, (addr>>8)%0xFF)
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yield TWrite(off+1, we+dat)
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yield TWrite(off+0, 0)
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for i in range(4):
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yield TWrite(off+i,0)
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def csr_transactions(trigger0, recorder0):
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# Trigger Prog
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##############################
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# Term Prog
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term_trans = []
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term_trans += [term_prog(trigger0.ports[0].reg_base, 0x00000000)]
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term_trans += [term_prog(trigger0.ports[1].reg_base, 0x00000004)]
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term_trans += [term_prog(trigger0.ports[2].reg_base, 0x00000008)]
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term_trans += [term_prog(trigger0.ports[3].reg_base, 0x0000000C)]
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for t in term_trans:
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for r in t:
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yield r
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# Sum Prog
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sum_tt = gen_truth_table("term0 | term1 | term2 | term3")
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sum_trans = []
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for i in range(len(sum_tt)):
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sum_trans.append(sum_prog(trigger0.sum.reg_base, i, sum_tt[i]))
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for t in sum_trans:
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for r in t:
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yield r
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# Recorder Prog
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##############################
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#Reset
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yield TWrite(recorder0.address + 0, 1)
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yield TWrite(recorder0.address + 0, 0)
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#Size
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yield TWrite(recorder0.address + 3, 0)
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yield TWrite(recorder0.address + 4, 64)
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#Offset
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yield TWrite(recorder0.address + 5, 0)
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yield TWrite(recorder0.address + 6, 16)
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#Arm
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yield TWrite(recorder0.address + 1, 1)
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# Wait Record to be done
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##############################
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global rec_done
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while not rec_done:
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yield None
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# Read recorded data
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##############################
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global dat_rdy
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for t in range(64):
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yield TWrite(recorder0.address + 7, 1)
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dat_rdy = False
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yield TWrite(recorder0.address + 7, 0)
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yield TRead(recorder0.address + 8)
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yield TRead(recorder0.address + 9)
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yield TRead(recorder0.address + 10)
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yield TRead(recorder0.address + 11)
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dat_rdy = True
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dat_rdy = False
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for t in range(512):
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yield None
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trig_sig_val = 0
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def main():
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# Trigger
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term0 = trigger.Term(32)
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term1 = trigger.Term(32)
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term2 = trigger.Term(32)
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term3 = trigger.Term(32)
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trigger0 = trigger.Trigger(TRIGGER_ADDR, 32, 64, [term0, term1, term2, term3])
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# Recorder
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recorder0 = recorder.Recorder(RECORDER_ADDR, 32, 1024)
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# Csr Master
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csr_master0 = csr.Initiator(csr_transactions(trigger0, recorder0))
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# Csr Interconnect
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csrcon0 = csr.Interconnect(csr_master0.bus,
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[
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trigger0.bank.interface,
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recorder0.bank.interface
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])
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trig_sig = Signal(BV(32))
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comb = []
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comb +=[
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trigger0.in_trig.eq(trig_sig)
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]
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comb += [
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recorder0.trig_dat.eq(trig_sig),
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recorder0.trig_hit.eq(trigger0.hit)
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]
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# Term Test
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def term_stimuli(s):
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global trig_sig_val
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s.wr(trig_sig,trig_sig_val)
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trig_sig_val += 1
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trig_sig_val = trig_sig_val % 256
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# Recorder Data
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def recorder_data(s):
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global rec_done
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if s.rd(recorder0.sequencer.rec_done) == 1:
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rec_done = True
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global dat_rdy
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if dat_rdy:
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print("%08X" %s.rd(recorder0._get_dat.field.w))
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global dat_vcd
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dat_vcd.append(s.rd(recorder0._get_dat.field.w))
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# Simulation
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def end_simulation(s):
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s.interrupt = csr_master0.done
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myvcd = Vcd()
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myvcd.add(Var("wire", 32, "trig_dat", dat_vcd))
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f = open("tb_Miscope_Out.vcd", "w")
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f.write(str(myvcd))
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f.close()
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fragment = autofragment.from_local()
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fragment += Fragment(comb=comb)
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fragment += Fragment(sim=[term_stimuli])
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fragment += Fragment(sim=[recorder_data])
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fragment += Fragment(sim=[end_simulation])
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sim = Simulator(fragment, Runner(),TopLevel("tb_MigScope.vcd"))
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sim.run(2000)
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main()
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input()
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