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af66ca7bad
litex
/
misoclib
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soc
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Florent Kermarrec
af66ca7bad
uart: add phy autodetect function
2015-03-06 10:19:29 +01:00
..
__init__.py
uart: add phy autodetect function
2015-03-06 10:19:29 +01:00
cpuif.py
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
2015-03-02 16:52:17 +01:00
sdram.py
targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
2015-03-06 07:56:45 +01:00