94 lines
3.2 KiB
Python
94 lines
3.2 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl.specials import Instance
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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class Clocking(Module, AutoCSR):
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def __init__(self, pads):
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self._r_pll_reset = CSRStorage()
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self._r_locked = CSRStatus()
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self.locked = Signal()
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self.serdesstrobe = Signal()
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self.clock_domains._cd_pix = ClockDomain()
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self.clock_domains._cd_pix5x = ClockDomain()
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self.clock_domains._cd_pix10x = ClockDomain()
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self.clock_domains._cd_pix20x = ClockDomain()
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###
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clk_dejitter = Signal()
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dcm_locked = Signal()
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self.specials += Instance("DCM_CLKGEN",
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Instance.Parameter("CLKIN_PERIOD", 26.7),
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Instance.Parameter("CLKFX_DIVIDE", 2),
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Instance.Parameter("CLKFX_MULTIPLY", 2),
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Instance.Parameter("CLKFX_MD_MAX", 1.0),
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Instance.Input("CLKIN", pads.clk),
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Instance.Input("RST", self._r_pll_reset.storage),
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Instance.Output("CLKFX", clk_dejitter),
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Instance.Output("LOCKED", dcm_locked)
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)
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clkfbout = Signal()
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pll_locked = Signal()
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pll_clk0 = Signal()
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pll_clk1 = Signal()
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pll_clk2 = Signal()
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pll_clk3 = Signal()
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self.specials += Instance("PLL_BASE",
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Instance.Parameter("CLKIN_PERIOD", 26.7),
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Instance.Parameter("CLKFBOUT_MULT", 20),
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Instance.Parameter("CLKOUT0_DIVIDE", 1), # pix20x
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Instance.Parameter("CLKOUT1_DIVIDE", 4), # pix5x
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Instance.Parameter("CLKOUT2_DIVIDE", 20), # pix
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Instance.Parameter("CLKOUT3_DIVIDE", 2), # pix10x
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Instance.Parameter("COMPENSATION", "INTERNAL"),
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Instance.Output("CLKFBOUT", clkfbout),
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# WARNING: Do not touch the order of those clocks, or PAR fails.
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Instance.Output("CLKOUT0", pll_clk0),
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Instance.Output("CLKOUT1", pll_clk1),
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Instance.Output("CLKOUT2", pll_clk2),
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Instance.Output("CLKOUT3", pll_clk3),
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Instance.Output("LOCKED", pll_locked),
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Instance.Input("CLKFBIN", clkfbout),
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Instance.Input("CLKIN", clk_dejitter),
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Instance.Input("RST", ~dcm_locked)
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)
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locked_async = Signal()
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self.specials += Instance("BUFPLL",
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Instance.Parameter("DIVIDE", 4),
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Instance.Input("PLLIN", pll_clk0),
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Instance.Input("GCLK", ClockSignal("pix5x")),
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Instance.Input("LOCKED", pll_locked),
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Instance.Output("IOCLK", self._cd_pix20x.clk),
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Instance.Output("LOCK", locked_async),
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Instance.Output("SERDESSTROBE", self.serdesstrobe)
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)
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self.specials += Instance("BUFG",
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Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
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self.specials += Instance("BUFG",
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Instance.Input("I", pll_clk2), Instance.Output("O", self._cd_pix.clk))
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self.specials += Instance("BUFG",
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Instance.Input("I", pll_clk3), Instance.Output("O", self._cd_pix10x.clk))
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self.specials += MultiReg(locked_async, self.locked, "sys")
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self.comb += self._r_locked.status.eq(self.locked)
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# sychronize pix+pix5x reset
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pix_rst_n = 1
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for i in range(2):
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new_pix_rst_n = Signal()
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self.specials += Instance("FDCE",
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Instance.Input("D", pix_rst_n),
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Instance.Input("CE", 1),
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Instance.Input("C", ClockSignal("pix")),
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Instance.Input("CLR", ~locked_async),
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Instance.Output("Q", new_pix_rst_n)
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)
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pix_rst_n = new_pix_rst_n
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self.comb += self._cd_pix.rst.eq(~pix_rst_n)
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self.comb += self._cd_pix5x.rst.eq(~pix_rst_n)
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