Jędrzej Boczar b0f8ee9876 litex_sim: add option to create SDRAM module from SPD data		2020-04-17 14:52:53 +02:00
..
boards	targets: manual define of the SDRAM PHY no longer needed.	2020-04-16 11:26:59 +02:00
build	build/generic_programmer: move requests import to do it only when needed.	2020-04-16 08:44:36 +02:00
gen	litex/build: move io.py from litex/gen and re-import DifferentialInput/Output, DDRInput/Output contributed to Migen.	2020-04-10 08:47:07 +02:00
soc	bios/sdram: update/simplify with new exported LiteDRAM parameters.	2020-04-16 10:42:01 +02:00
tools	litex_sim: add option to create SDRAM module from SPD data	2020-04-17 14:52:53 +02:00
__init__.py	soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)	2019-09-30 23:41:07 +02:00