Florent Kermarrec d20b9c2221 uart: pass *args, **kwargs to sim phy		2015-03-06 12:08:10 +01:00
..
phy	uart: pass *args, **kwargs to sim phy	2015-03-06 12:08:10 +01:00
test	uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)	2015-03-01 12:14:34 +01:00
__init__.py	uart: generate ack for rx (serialboot OK with sim)	2015-03-04 00:57:37 +01:00