355 lines
12 KiB
Verilog
355 lines
12 KiB
Verilog
// ==================================================================
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// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
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// ------------------------------------------------------------------
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// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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// ALL RIGHTS RESERVED
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// ------------------------------------------------------------------
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//
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// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
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//
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// Permission:
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//
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// Lattice Semiconductor grants permission to use this code
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// pursuant to the terms of the Lattice Semiconductor Corporation
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// Open Source License Agreement.
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//
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// Disclaimer:
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//
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// Lattice Semiconductor provides no warranty regarding the use or
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// functionality of this code. It is the user's responsibility to
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// verify the user's design for consistency and functionality through
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// the use of formal verification methods.
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//
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// --------------------------------------------------------------------
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//
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// Lattice Semiconductor Corporation
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// 5555 NE Moore Court
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// Hillsboro, OR 97214
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// U.S.A
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//
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// TEL: 1-800-Lattice (USA and Canada)
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// 503-286-8001 (other locations)
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//
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// web: http://www.latticesemi.com/
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// email: techsupport@latticesemi.com
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//
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// --------------------------------------------------------------------
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// FILE DETAILS
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// Project : LatticeMico32
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// File : lm32_top.v
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// Title : Top-level of CPU.
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// Dependencies : lm32_include.v
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// Version : 6.1.17
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// : removed SPI - 04/12/07
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// Version : 7.0SP2, 3.0
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// : No Change
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// Version : 3.1
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// : No Change
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// =============================================================================
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`include "lm32_include.v"
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/////////////////////////////////////////////////////
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// Module interface
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/////////////////////////////////////////////////////
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module lm32_top (
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// ----- Inputs -------
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clk_i,
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rst_i,
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`ifdef CFG_DEBUG_ENABLED
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`ifdef CFG_ALTERNATE_EBA
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at_debug,
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`endif
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`endif
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// From external devices
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`ifdef CFG_INTERRUPTS_ENABLED
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interrupt,
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`endif
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// From user logic
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`ifdef CFG_USER_ENABLED
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user_result,
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user_complete,
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`endif
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`ifdef CFG_IWB_ENABLED
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// Instruction Wishbone master
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I_DAT_I,
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I_ACK_I,
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I_ERR_I,
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I_RTY_I,
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`endif
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`ifdef CFG_EXTERNAL_BREAK_ENABLED
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ext_break,
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`endif
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// Data Wishbone master
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D_DAT_I,
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D_ACK_I,
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D_ERR_I,
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D_RTY_I,
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// ----- Outputs -------
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`ifdef CFG_USER_ENABLED
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user_valid,
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user_opcode,
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user_operand_0,
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user_operand_1,
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`endif
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`ifdef CFG_IWB_ENABLED
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// Instruction Wishbone master
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I_DAT_O,
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I_ADR_O,
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I_CYC_O,
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I_SEL_O,
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I_STB_O,
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I_WE_O,
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I_CTI_O,
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I_LOCK_O,
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I_BTE_O,
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`endif
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// Data Wishbone master
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D_DAT_O,
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D_ADR_O,
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D_CYC_O,
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D_SEL_O,
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D_STB_O,
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D_WE_O,
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D_CTI_O,
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D_LOCK_O,
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D_BTE_O
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);
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/////////////////////////////////////////////////////
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// Inputs
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/////////////////////////////////////////////////////
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input clk_i; // Clock
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input rst_i; // Reset
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`ifdef CFG_DEBUG_ENABLED
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`ifdef CFG_ALTERNATE_EBA
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input at_debug; // GPIO input that maps EBA to DEBA
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`endif
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`endif
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`ifdef CFG_INTERRUPTS_ENABLED
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input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
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`endif
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`ifdef CFG_USER_ENABLED
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input [`LM32_WORD_RNG] user_result; // User-defined instruction result
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input user_complete; // Indicates the user-defined instruction result is valid
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`endif
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`ifdef CFG_IWB_ENABLED
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input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
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input I_ACK_I; // Instruction Wishbone interface acknowledgement
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input I_ERR_I; // Instruction Wishbone interface error
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input I_RTY_I; // Instruction Wishbone interface retry
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`endif
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input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
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input D_ACK_I; // Data Wishbone interface acknowledgement
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input D_ERR_I; // Data Wishbone interface error
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input D_RTY_I; // Data Wishbone interface retry
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`ifdef CFG_EXTERNAL_BREAK_ENABLED
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input ext_break;
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`endif
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/////////////////////////////////////////////////////
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// Outputs
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/////////////////////////////////////////////////////
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`ifdef CFG_USER_ENABLED
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output user_valid; // Indicates that user_opcode and user_operand_* are valid
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wire user_valid;
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output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
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reg [`LM32_USER_OPCODE_RNG] user_opcode;
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output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
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wire [`LM32_WORD_RNG] user_operand_0;
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output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
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wire [`LM32_WORD_RNG] user_operand_1;
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`endif
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`ifdef CFG_IWB_ENABLED
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output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
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wire [`LM32_WORD_RNG] I_DAT_O;
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output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
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wire [`LM32_WORD_RNG] I_ADR_O;
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output I_CYC_O; // Instruction Wishbone interface cycle
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wire I_CYC_O;
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output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
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wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
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output I_STB_O; // Instruction Wishbone interface strobe
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wire I_STB_O;
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output I_WE_O; // Instruction Wishbone interface write enable
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wire I_WE_O;
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output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
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wire [`LM32_CTYPE_RNG] I_CTI_O;
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output I_LOCK_O; // Instruction Wishbone interface lock bus
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wire I_LOCK_O;
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output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
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wire [`LM32_BTYPE_RNG] I_BTE_O;
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`endif
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output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
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wire [`LM32_WORD_RNG] D_DAT_O;
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output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
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wire [`LM32_WORD_RNG] D_ADR_O;
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output D_CYC_O; // Data Wishbone interface cycle
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wire D_CYC_O;
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output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
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wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
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output D_STB_O; // Data Wishbone interface strobe
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wire D_STB_O;
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output D_WE_O; // Data Wishbone interface write enable
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wire D_WE_O;
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output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
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wire [`LM32_CTYPE_RNG] D_CTI_O;
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output D_LOCK_O; // Date Wishbone interface lock bus
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wire D_LOCK_O;
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output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
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wire [`LM32_BTYPE_RNG] D_BTE_O;
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/////////////////////////////////////////////////////
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// Internal nets and registers
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/////////////////////////////////////////////////////
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`ifdef CFG_JTAG_ENABLED
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// Signals between JTAG interface and CPU
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wire [`LM32_BYTE_RNG] jtag_reg_d;
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wire [`LM32_BYTE_RNG] jtag_reg_q;
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wire jtag_update;
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wire [2:0] jtag_reg_addr_d;
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wire [2:0] jtag_reg_addr_q;
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wire jtck;
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wire jrstn;
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`endif
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// TODO: get the trace signals out
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`ifdef CFG_TRACE_ENABLED
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// PC trace signals
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wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
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wire trace_pc_valid; // Indicates that a new trace PC is valid
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wire trace_exception; // Indicates an exception has occured
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wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
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wire trace_eret; // Indicates an eret instruction has been executed
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`ifdef CFG_DEBUG_ENABLED
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wire trace_bret; // Indicates a bret instruction has been executed
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`endif
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`endif
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/////////////////////////////////////////////////////
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// Functions
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/////////////////////////////////////////////////////
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`include "lm32_functions.v"
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/////////////////////////////////////////////////////
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// Instantiations
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/////////////////////////////////////////////////////
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// LM32 CPU
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lm32_cpu cpu (
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// ----- Inputs -------
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.clk_i (clk_i),
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`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
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.clk_n_i (clk_n),
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`endif
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.rst_i (rst_i),
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`ifdef CFG_DEBUG_ENABLED
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`ifdef CFG_ALTERNATE_EBA
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.at_debug (at_debug),
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`endif
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`endif
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// From external devices
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`ifdef CFG_INTERRUPTS_ENABLED
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.interrupt (interrupt),
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`endif
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// From user logic
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`ifdef CFG_USER_ENABLED
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.user_result (user_result),
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.user_complete (user_complete),
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`endif
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`ifdef CFG_JTAG_ENABLED
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// From JTAG
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.jtag_clk (jtck),
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.jtag_update (jtag_update),
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.jtag_reg_q (jtag_reg_q),
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.jtag_reg_addr_q (jtag_reg_addr_q),
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`endif
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`ifdef CFG_EXTERNAL_BREAK_ENABLED
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.ext_break (ext_break),
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`endif
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`ifdef CFG_IWB_ENABLED
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// Instruction Wishbone master
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.I_DAT_I (I_DAT_I),
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.I_ACK_I (I_ACK_I),
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.I_ERR_I (I_ERR_I),
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.I_RTY_I (I_RTY_I),
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`endif
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// Data Wishbone master
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.D_DAT_I (D_DAT_I),
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.D_ACK_I (D_ACK_I),
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.D_ERR_I (D_ERR_I),
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.D_RTY_I (D_RTY_I),
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// ----- Outputs -------
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`ifdef CFG_TRACE_ENABLED
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.trace_pc (trace_pc),
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.trace_pc_valid (trace_pc_valid),
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.trace_exception (trace_exception),
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.trace_eid (trace_eid),
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.trace_eret (trace_eret),
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`ifdef CFG_DEBUG_ENABLED
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.trace_bret (trace_bret),
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`endif
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`endif
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`ifdef CFG_JTAG_ENABLED
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.jtag_reg_d (jtag_reg_d),
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.jtag_reg_addr_d (jtag_reg_addr_d),
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`endif
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`ifdef CFG_USER_ENABLED
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.user_valid (user_valid),
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.user_opcode (user_opcode),
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.user_operand_0 (user_operand_0),
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.user_operand_1 (user_operand_1),
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`endif
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`ifdef CFG_IWB_ENABLED
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// Instruction Wishbone master
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.I_DAT_O (I_DAT_O),
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.I_ADR_O (I_ADR_O),
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.I_CYC_O (I_CYC_O),
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.I_SEL_O (I_SEL_O),
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.I_STB_O (I_STB_O),
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.I_WE_O (I_WE_O),
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.I_CTI_O (I_CTI_O),
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.I_LOCK_O (I_LOCK_O),
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.I_BTE_O (I_BTE_O),
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`endif
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// Data Wishbone master
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.D_DAT_O (D_DAT_O),
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.D_ADR_O (D_ADR_O),
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.D_CYC_O (D_CYC_O),
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.D_SEL_O (D_SEL_O),
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.D_STB_O (D_STB_O),
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.D_WE_O (D_WE_O),
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.D_CTI_O (D_CTI_O),
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.D_LOCK_O (D_LOCK_O),
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.D_BTE_O (D_BTE_O)
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);
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`ifdef CFG_JTAG_ENABLED
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// JTAG cores
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jtag_cores jtag_cores (
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// ----- Inputs -----
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.reg_d (jtag_reg_d),
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.reg_addr_d (jtag_reg_addr_d),
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// ----- Outputs -----
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.reg_update (jtag_update),
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.reg_q (jtag_reg_q),
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.reg_addr_q (jtag_reg_addr_q),
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.jtck (jtck),
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.jrstn (jrstn)
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);
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`endif
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endmodule
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