233 lines
6.3 KiB
Python
233 lines
6.3 KiB
Python
from functools import partial
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from migen.fhdl.structure import *
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from migen.fhdl.structure import _Operator, _Slice, _Assign, _StatementList
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from migen.fhdl.tools import *
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from migen.fhdl.namer import Namespace, build_namespace
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def _printsig(ns, s):
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if s.bv.signed:
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n = "signed "
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else:
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n = ""
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if s.bv.width > 1:
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n += "[" + str(s.bv.width-1) + ":0] "
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n += ns.get_name(s)
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return n
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def _printexpr(ns, node):
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if isinstance(node, Constant):
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if node.n >= 0:
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return str(node.bv) + str(node.n)
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else:
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return "-" + str(node.bv) + str(-self.n)
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elif isinstance(node, Signal):
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return ns.get_name(node)
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elif isinstance(node, _Operator):
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arity = len(node.operands)
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if arity == 1:
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r = node.op + _printexpr(ns, node.operands[0])
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elif arity == 2:
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r = _printexpr(ns, node.operands[0]) + " " + node.op + " " + _printexpr(ns, node.operands[1])
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else:
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raise TypeError
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return "(" + r + ")"
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elif isinstance(node, _Slice):
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if node.start + 1 == node.stop:
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sr = "[" + str(node.start) + "]"
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else:
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sr = "[" + str(node.stop-1) + ":" + str(node.start) + "]"
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return _printexpr(ns, node.value) + sr
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elif isinstance(node, Cat):
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l = list(map(partial(_printexpr, ns), node.l))
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l.reverse()
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return "{" + ", ".join(l) + "}"
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elif isinstance(node, Replicate):
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return "{" + str(node.n) + "{" + _printexpr(ns, node.v) + "}}"
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else:
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raise TypeError
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(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
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def _printnode(ns, at, level, node):
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if node is None:
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return ""
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elif isinstance(node, _Assign):
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if at == _AT_BLOCKING:
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assignment = " = "
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elif at == _AT_NONBLOCKING:
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assignment = " <= "
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elif is_variable(node.l):
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assignment = " = "
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else:
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assignment = " <= "
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return "\t"*level + _printexpr(ns, node.l) + assignment + _printexpr(ns, node.r) + ";\n"
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elif isinstance(node, _StatementList):
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return "".join(list(map(partial(_printnode, ns, at, level), node.l)))
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elif isinstance(node, If):
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r = "\t"*level + "if (" + _printexpr(ns, node.cond) + ") begin\n"
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r += _printnode(ns, at, level + 1, node.t)
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if node.f.l:
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r += "\t"*level + "end else begin\n"
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r += _printnode(ns, at, level + 1, node.f)
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r += "\t"*level + "end\n"
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return r
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elif isinstance(node, Case):
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r = "\t"*level + "case (" + _printexpr(ns, node.test) + ")\n"
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for case in node.cases:
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r += "\t"*(level + 1) + _printexpr(ns, case[0]) + ": begin\n"
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r += _printnode(ns, at, level + 2, case[1])
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r += "\t"*(level + 1) + "end\n"
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if node.default.l:
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r += "\t"*(level + 1) + "default: begin\n"
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r += _printnode(ns, at, level + 2, node.default)
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r += "\t"*(level + 1) + "end\n"
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r += "\t"*level + "endcase\n"
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return r
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else:
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raise TypeError
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def _list_comb_wires(f):
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r = set()
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groups = group_by_targets(f.comb)
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for g in groups:
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if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
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r |= g[0]
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return r
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def _printheader(f, ios, name, ns):
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sigs = list_signals(f)
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targets = list_targets(f)
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instouts = list_inst_ios(f, False, True)
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wires = _list_comb_wires(f)
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r = "module " + name + "(\n"
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firstp = True
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for sig in ios:
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if not firstp:
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r += ",\n"
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firstp = False
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if sig in targets:
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if sig in wires:
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r += "\toutput " + _printsig(ns, sig)
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else:
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r += "\toutput reg " + _printsig(ns, sig)
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elif sig in instouts:
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r += "\toutput " + _printsig(ns, sig)
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else:
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r += "\tinput " + _printsig(ns, sig)
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r += "\n);\n\n"
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for sig in sigs - ios:
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if sig in wires or sig in instouts:
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r += "wire " + _printsig(ns, sig) + ";\n"
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else:
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r += "reg " + _printsig(ns, sig) + ";\n"
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r += "\n"
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return r
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def _printcomb(f, ns):
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r = ""
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if f.comb.l:
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# Generate a dummy event to get the simulator
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# to run the combinatorial process once at the beginning.
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syn_off = "// synthesis translate off\n"
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syn_on = "// synthesis translate on\n"
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dummy_s = Signal(name_override="dummy_s")
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r += syn_off
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r += "reg " + _printsig(ns, dummy_s) + ";\n"
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r += "initial " + ns.get_name(dummy_s) + " <= 1'b0;\n"
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r += syn_on
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groups = group_by_targets(f.comb)
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for g in groups:
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if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
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r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
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else:
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dummy_d = Signal(name_override="dummy_d")
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r += "\n" + syn_off
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r += "reg " + _printsig(ns, dummy_d) + ";\n"
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r += syn_on
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r += "always @(*) begin\n"
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for t in g[0]:
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r += "\t" + ns.get_name(t) + " <= " + str(t.reset) + ";\n"
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r += _printnode(ns, _AT_NONBLOCKING, 1, _StatementList(g[1]))
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r += syn_off
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r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
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r += syn_on
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r += "end\n"
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r += "\n"
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return r
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def _printsync(f, ns, clk_signal, rst_signal):
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r = ""
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if f.sync.l:
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r += "always @(posedge " + ns.get_name(clk_signal) + ") begin\n"
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r += _printnode(ns, _AT_SIGNAL, 1, insert_reset(rst_signal, f.sync))
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r += "end\n\n"
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return r
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def _printinstances(ns, i, clk, rst):
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r = ""
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for x in i:
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r += x.of + " "
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if x.parameters:
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r += "#(\n"
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firstp = True
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for p in x.parameters:
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if not firstp:
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r += ",\n"
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firstp = False
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r += "\t." + p[0] + "("
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if isinstance(p[1], int) or isinstance(p[1], float) or isinstance(p[1], Constant):
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r += str(p[1])
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elif isinstance(p[1], str):
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r += "\"" + p[1] + "\""
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else:
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raise TypeError
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r += ")"
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r += "\n) "
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r += ns.get_name(x)
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if x.parameters: r += " "
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r += "(\n"
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ports = list(x.ins.items()) + list(x.outs.items())
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if x.clkport:
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ports.append((x.clkport, clk))
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if x.rstport:
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ports.append((x.rstport, rst))
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firstp = True
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for p in ports:
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if not firstp:
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r += ",\n"
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firstp = False
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r += "\t." + p[0] + "(" + ns.get_name(p[1]) + ")"
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if not firstp:
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r += "\n"
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r += ");\n\n"
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return r
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def convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, return_ns=False):
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if clk_signal is None:
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clk_signal = Signal(name_override="sys_clk")
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ios.add(clk_signal)
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if rst_signal is None:
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rst_signal = Signal(name_override="sys_rst")
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ios.add(rst_signal)
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ios |= f.pads
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ns = build_namespace(list_signals(f) | list_inst_ios(f, True, True) | ios)
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r = "/* Machine-generated using Migen */\n"
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r += _printheader(f, ios, name, ns)
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r += _printcomb(f, ns)
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r += _printsync(f, ns, clk_signal, rst_signal)
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r += _printinstances(ns, f.instances, clk_signal, rst_signal)
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r += "endmodule\n"
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if return_ns:
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return r, ns
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else:
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return r
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