45 lines
1.1 KiB
Python
45 lines
1.1 KiB
Python
from migen.genlib.resetsync import AsyncResetSynchronizer
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from litesata.common import *
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from litesata.phy import LiteSATAPHY
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from litesata import LiteSATA
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class LiteSATACore(Module):
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default_platform = "verilog_backend"
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def __init__(self, platform, clk_freq=166*1000000, nports=4):
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self.clk_freq = clk_freq
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# SATA PHY/Core/Frontend
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self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
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self.submodules.sata = LiteSATA(self.sata_phy)
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# Get user ports from crossbar
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self.user_ports = self.sata.crossbar.get_ports(nports)
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def get_ios(self):
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ios = set()
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# Transceiver
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for e in dir(self.sata_phy.pads):
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obj = getattr(self.sata_phy.pads, e)
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if isinstance(obj, Signal):
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ios = ios.union({obj})
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# User ports
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def _iter_layout(layout):
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for e in layout:
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if isinstance(e[1], list):
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yield from _iter_layout(e[1])
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else:
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yield e
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for port in self.user_ports:
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for endpoint in [port.sink, port.source]:
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for e in _iter_layout(endpoint.layout):
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obj = getattr(endpoint, e[0])
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ios = ios.union({obj})
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return ios
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default_subtarget = LiteSATACore
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