litex/misoclib/soc
2015-03-29 12:34:40 +02:00
..
__init__.py rename sdram mapping to main_ram 2015-03-21 21:01:46 +01:00
cpuif.py cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) 2015-03-02 16:52:17 +01:00
sdram.py sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0) 2015-03-29 12:34:40 +02:00