116 lines
4.1 KiB
Python
Executable File
116 lines
4.1 KiB
Python
Executable File
#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.build.platforms import de0nano
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from misoc.cores.sdram_settings import IS42S16160
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from misoc.cores.sdram_phy import GENSDRPHY
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from misoc.integration.soc_sdram import *
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from misoc.integration.builder import *
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class _PLL(Module):
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def __init__(self, period_in, name, phase_shift, operation_mode):
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self.clk_in = Signal()
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self.clk_out = Signal()
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self.specials += Instance("ALTPLL",
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p_bandwidth_type = "AUTO",
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p_clk0_divide_by = 1,
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p_clk0_duty_cycle = 50,
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p_clk0_multiply_by = 2,
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p_clk0_phase_shift = "{}".format(str(phase_shift)),
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p_compensate_clock = "CLK0",
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p_inclk0_input_frequency = int(period_in*1000),
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p_intended_device_family = "Cyclone IV E",
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p_lpm_hint = "CBX_MODULE_PREFIX={}_pll".format(name),
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p_lpm_type = "altpll",
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p_operation_mode = operation_mode,
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i_inclk=self.clk_in,
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o_clk=self.clk_out,
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i_areset=0,
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i_clkena=0x3f,
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i_clkswitch=0,
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i_configupdate=0,
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i_extclkena=0xf,
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i_fbin=1,
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i_pfdena=1,
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i_phasecounterselect=0xf,
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i_phasestep=1,
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i_phaseupdown=1,
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i_pllena=1,
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i_scanaclr=0,
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i_scanclk=0,
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i_scanclkena=1,
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i_scandata=0,
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i_scanread=0,
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i_scanwrite=0
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)
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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clk50 = platform.request("clk50")
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sys_pll = _PLL(20, "sys", 0, "NORMAL")
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self.submodules += sys_pll
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self.comb += [
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sys_pll.clk_in.eq(clk50),
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self.cd_sys.clk.eq(sys_pll.clk_out)
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]
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sdram_pll = _PLL(20, "sdram", -3000, "ZERO_DELAY_BUFFER")
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self.submodules += sdram_pll
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self.comb += [
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sdram_pll.clk_in.eq(clk50),
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self.cd_sys_ps.clk.eq(sdram_pll.clk_out)
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]
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# Power on Reset (vendor agnostic)
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rst_n = Signal()
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self.sync.por += rst_n.eq(1)
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(~rst_n),
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self.cd_sys_ps.rst.eq(~rst_n)
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]
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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class BaseSoC(SoCSDRAM):
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def __init__(self, **kwargs):
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platform = de0nano.Platform()
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SoCSDRAM.__init__(self, platform,
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clk_freq=100*1000000,
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integrated_rom_size=0x8000,
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**kwargs)
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self.submodules.crg = _CRG(platform)
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if not self.integrated_main_ram_size:
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = IS42S16160(self.clk_freq)
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self.register_sdram(self.sdrphy, "minicon",
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sdram_module.geom_settings, sdram_module.timing_settings)
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def main():
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parser = argparse.ArgumentParser(description="MiSoC port to the Altera DE0 Nano")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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