73 lines
1.9 KiB
Python
73 lines
1.9 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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import sys
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sys.path.append("../../../")
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from migScope import trigger, recorder, migIo, migLa
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from migScope.tools.truthtable import *
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from migScope.tools.vcd import *
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import spi2Csr
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from spi2Csr.tools.uart2Spi import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Bus Width
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trig_width = 32
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dat_width = 32
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# Record Size
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record_size = 4096
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# Csr Addr
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MIGIO0_ADDR = 0x0000
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MIGLA1_ADDR = 0x0600
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csr = Uart2Spi(1,115200,debug=False)
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# MigScope Configuration
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# migIo0
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migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr)
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# migIla1
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term1 = trigger.Term(trig_width)
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trigger1 = trigger.Trigger(trig_width, [term1])
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recorder1 = recorder.Recorder(dat_width, record_size)
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migLa1 = migLa.MigLa(MIGLA1_ADDR, trigger1, recorder1, csr)
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#==============================================================================
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# T E S T M I G L A
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#==============================================================================
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dat_vcd = []
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recorder1.size(1024)
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term1.write(0x0100005A,0x0100005A)
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sum_tt = gen_truth_table("term1")
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migLa1.trig.sum.write(sum_tt)
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migLa1.rec.reset()
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migLa1.rec.offset(256)
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migLa1.rec.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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csr.write(0x0000,0x5A)
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while(not migLa1.rec.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += migLa1.rec.read(1024)
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print("[Done]")
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myvcd = Vcd()
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myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8)))
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myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24)))
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myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24)))
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myvcd.write("test_MigLa_1.vcd") |