Sebastien Bourdeauducq b4e041ecf1 s6ddrphy: write path OK in simulation		2012-02-20 23:55:20 +01:00
..
dfii	Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.	2012-02-18 18:12:14 +01:00
lm32	lm32: compatibility with the new instance API	2012-02-16 18:35:22 +01:00
m1crg	s6ddrphy: write path OK in simulation	2012-02-20 23:55:20 +01:00
norflash	Use new bus API	2012-02-15 16:55:13 +01:00
s6ddrphy	s6ddrphy: write path OK in simulation	2012-02-20 23:55:20 +01:00
sram	Use new bus API	2012-02-15 16:55:13 +01:00
uart	uart: RX support	2012-02-07 14:12:23 +01:00
__init__.py	Initial import	2011-12-13 17:33:12 +01:00