Florent Kermarrec b4ba2a47ef soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover		2020-01-17 06:32:00 +01:00
..
cores	soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover	2020-01-17 06:32:00 +01:00
integration	SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args.	2020-01-15 10:59:01 +01:00
interconnect	soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.	2020-01-16 09:46:54 +01:00
software	bios/sdram: switch to updated CSR accessors, and misc. cleanup	2020-01-13 10:09:02 -05:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00