Jędrzej Boczar b4c1120e3d soc/integration: choose interconnect based on bus standard		2020-07-22 17:16:07 +02:00
..
cores	cpu/vexriscv/system.h: update flush_cpu_dcache.	2020-07-21 19:43:00 +02:00
doc	soc/doc/csr: allow CSRField.reset to be a Migen Constant.	2020-03-23 18:47:41 +01:00
integration	soc/integration: choose interconnect based on bus standard	2020-07-22 17:16:07 +02:00
interconnect	soc/integration: choose interconnect based on bus standard	2020-07-22 17:16:07 +02:00
software	software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz.	2020-07-20 13:48:49 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00