Florent Kermarrec b509068790 cores/clock: add logging to visualize clkin/clkouts and computed config.		2020-03-10 11:13:16 +01:00
..
cores	cores/clock: add logging to visualize clkin/clkouts and computed config.	2020-03-10 11:13:16 +01:00
doc	Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression.	2020-03-06 14:12:58 +01:00
integration	integration/soc: add FPGA device and System clock to logs.	2020-03-10 11:10:23 +01:00
interconnect	Fix copyrights	2020-03-05 17:44:10 +01:00
software	software/common: fix LTO checks.	2020-03-09 19:08:27 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00