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https://github.com/enjoy-digital/litex.git
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ce49990084
This commit: * adds the support for I2S standard mode, * extends I2S left justified mode, * allows to configure sample size for tx/rx in 1-32 bits range, * implements I2S master mode, * allows to concatenate channels or used the padded mode. This required to rework the FSM.
15 lines
372 B
Python
15 lines
372 B
Python
# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import unittest
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from migen import *
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from litex.soc.cores.i2s import S7I2S
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class TestI2S(unittest.TestCase):
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def test_s7i2sslave_syntax(self):
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i2s_pads = Record([("rx", 1), ("tx", 1), ("sync", 1), ("clk", 1)])
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i2s = S7I2S(pads=i2s_pads, fifo_depth=256)
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