154 lines
3.5 KiB
Python
154 lines
3.5 KiB
Python
from migen.fhdl.std import *
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from migen.actorlib.structuring import *
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from migen.genlib.fsm import FSM, NextState
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from liteusb.ftdi.std import *
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class FtdiDepacketizer(Module):
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def __init__(self, timeout=10):
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self.sink = sink = Sink(phy_layout)
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self.source = source = Source(user_layout)
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# Packet description
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# - preamble : 4 bytes
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# - dst : 1 byte
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# - length : 4 bytes
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# - payload
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preamble = Array(Signal(8) for i in range(4))
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header = [
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# dst
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source.dst,
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# length
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source.length[24:32],
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source.length[16:24],
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source.length[8:16],
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source.length[0:8],
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]
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header_pack = InsertReset(Pack(phy_layout, len(header)))
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self.submodules += header_pack
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for i, byte in enumerate(header):
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chunk = getattr(header_pack.source.payload, "chunk" + str(i))
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self.comb += byte.eq(chunk.d)
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fsm = FSM()
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self.submodules += fsm
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self.comb += preamble[0].eq(sink.d)
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for i in range(1, 4):
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self.sync += If(sink.stb & sink.ack,
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preamble[i].eq(preamble[i-1])
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)
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fsm.act("WAIT_SOP",
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If( (preamble[3] == 0x5A) &
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(preamble[2] == 0xA5) &
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(preamble[1] == 0x5A) &
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(preamble[0] == 0xA5) &
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sink.stb,
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NextState("RECEIVE_HEADER")
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),
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sink.ack.eq(1),
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header_pack.source.ack.eq(1),
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)
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self.submodules.timeout = FtdiTimeout(60000000, timeout)
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self.comb += self.timeout.clear.eq(fsm.ongoing("WAIT_SOP"))
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fsm.act("RECEIVE_HEADER",
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header_pack.sink.stb.eq(sink.stb),
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header_pack.sink.payload.eq(sink.payload),
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If(self.timeout.done, NextState("WAIT_SOP"))
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.Elif(header_pack.source.stb, NextState("RECEIVE_PAYLOAD"))
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.Else(sink.ack.eq(1))
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)
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self.comb += header_pack.reset.eq(self.timeout.done)
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sop = Signal()
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eop = Signal()
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cnt = Signal(32)
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fsm.act("RECEIVE_PAYLOAD",
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source.stb.eq(sink.stb),
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source.sop.eq(sop),
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source.eop.eq(eop),
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source.d.eq(sink.d),
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sink.ack.eq(source.ack),
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If((eop & sink.stb & source.ack) | self.timeout.done, NextState("WAIT_SOP"))
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)
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self.sync += \
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If(fsm.ongoing("WAIT_SOP"),
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cnt.eq(0)
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).Elif(source.stb & source.ack,
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cnt.eq(cnt + 1)
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)
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self.comb += sop.eq(cnt == 0)
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self.comb += eop.eq(cnt == source.length - 1)
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#
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# TB
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#
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src_data = [
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0x5A, 0xA5, 0x5A, 0xA5, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x02, 0x03,
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0x5A, 0xA5, 0x5A, 0xA5, 0x12, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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]*4
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class DepacketizerSourceModel(Module, Source, RandRun):
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def __init__(self, data):
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Source.__init__(self, phy_layout)
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RandRun.__init__(self, 50)
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self.data = data
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self._stb = 0
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self._cnt = 0
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def do_simulation(self, selfp):
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RandRun.do_simulation(self, selfp)
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if self.run and not self._stb:
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self._stb = 1
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if selfp.stb and selfp.ack:
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self._cnt +=1
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selfp.stb = self._stb
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selfp.d = self.data[self._cnt]
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if self._cnt == len(self.data)-1:
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raise StopSimulation
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class DepacketizerSinkModel(Module, Sink, RandRun):
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def __init__(self):
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Sink.__init__(self, user_layout, True)
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RandRun.__init__(self, 50)
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def do_simulation(self, selfp):
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RandRun.do_simulation(self, selfp)
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if self.run:
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selfp.ack = 1
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else:
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selfp.ack = 0
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class TB(Module):
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def __init__(self):
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self.submodules.source = DepacketizerSourceModel(src_data)
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self.submodules.dut = FtdiDepacketizer()
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self.submodules.sink = DepacketizerSinkModel()
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self.comb += [
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self.source.connect(self.dut.sink),
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self.dut.source.connect(self.sink),
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]
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def main():
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from migen.sim.generic import run_simulation
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run_simulation(TB(), ncycles=400, vcd_name="tb_depacketizer.vcd")
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if __name__ == "__main__":
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main()
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