mirror of
https://github.com/enjoy-digital/litex.git
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110 lines
2.8 KiB
Python
110 lines
2.8 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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from migen.sim.generic import Simulator, PureSimulable, TopLevel
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from migen.sim.icarus import Runner
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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import sys
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sys.path.append("../")
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import spi2Csr
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def get_bit(dat, bit):
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return int(dat & (1<<bit) != 0)
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def spi_transactions():
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yield TWrite(0xA5A5,1)
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yield TWrite(0x5A5A,2)
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yield TWrite(0xA5A5,3)
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yield TWrite(0x5A5A,4)
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class SpiMaster(PureSimulable):
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def __init__(self, spi, generator):
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self.spi = spi
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self.generator = generator
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self.transaction_start = 0
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self.transaction = None
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self.done = False
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def do_simulation(self, s):
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a_w = self.spi.a_width
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d_w = self.spi.d_width
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if not self.done:
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if self.transaction is None:
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try:
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self.transaction = next(self.generator)
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except StopIteration:
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self.done = True
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self.transaction = None
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if self.transaction is not None:
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self.transaction_cnt = 0
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elif isinstance(self.transaction,TWrite):
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# Clk
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if self.transaction_cnt%2:
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s.wr(self.spi.spi_clk,1)
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else:
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s.wr(self.spi.spi_clk,0)
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# Mosi Addr
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if self.transaction_cnt < a_w*2-1:
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bit = a_w-1-int((self.transaction_cnt)/2)
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data = get_bit(self.transaction.address,bit)
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s.wr(self.spi.spi_mosi,data)
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# Mosi Data
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if self.transaction_cnt > a_w*2 and self.transaction_cnt < a_w*2+d_w*2-1:
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bit = d_w-1-int((self.transaction_cnt-a_w*2)/2)
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data = get_bit(self.transaction.data,bit)
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s.wr(self.spi.spi_mosi,data)
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# Cs_n
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if self.transaction_cnt < a_w*2+d_w*2:
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s.wr(self.spi.spi_cs_n,0)
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else:
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s.wr(self.spi.spi_cs_n,1)
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s.wr(self.spi.spi_clk,0)
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s.wr(self.spi.spi_mosi,0)
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self.transaction = None
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# Incr transaction_cnt
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self.transaction_cnt +=1
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def main():
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# Csr Slave
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scratch_reg0 = RegisterField("scratch_reg0", 32, reset=0,access_dev=READ_ONLY)
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scratch_reg1 = RegisterField("scratch_reg1", 32, reset=0,access_dev=READ_ONLY)
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scratch_reg2 = RegisterField("scratch_reg3", 32, reset=0,access_dev=READ_ONLY)
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scratch_reg3 = RegisterField("scratch_reg4", 32, reset=0,access_dev=READ_ONLY)
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regs = [scratch_reg0,scratch_reg1,scratch_reg2,scratch_reg3]
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bank0 = csrgen.Bank([scratch_reg0,],address=0x0000)
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# Spi2Csr
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spi2csr0 = spi2Csr.Spi2Csr(16,8)
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# Csr Interconnect
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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bank0.interface
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])
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# Spi Master
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spi_master0 = SpiMaster(spi2csr0,spi_transactions())
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# Simulation
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def end_simulation(s):
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s.interrupt = spi_master0.done
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fragment = autofragment.from_local()
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fragment += Fragment(sim=[end_simulation])
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sim = Simulator(fragment, Runner(),TopLevel("tb_spi2Csr.vcd"))
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sim.run(1000)
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main()
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input()
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