30 lines
803 B
Python
30 lines
803 B
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from misoclib.gensoc import GenSoC, mem_decoder
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class _CRG(Module):
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def __init__(self, clk_in):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# Power on Reset (vendor agnostic)
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rst_n = Signal()
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self.sync.por += rst_n.eq(1)
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self.comb += [
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self.cd_sys.clk.eq(clk_in),
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self.cd_por.clk.eq(clk_in),
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self.cd_sys.rst.eq(~rst_n)
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]
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class SimpleSoC(GenSoC):
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def __init__(self, platform, **kwargs):
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GenSoC.__init__(self, platform,
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clk_freq=int((1/(platform.default_clk_period))*1000000000),
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with_rom=True,
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with_sdram=True, sdram_size=16*1024,
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**kwargs)
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self.submodules.crg = _CRG(platform.request(platform.default_clk_name))
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default_subtarget = SimpleSoC
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