290 lines
6.6 KiB
Python
290 lines
6.6 KiB
Python
from litescope.common import *
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from migen.bus import wishbone
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from migen.genlib.misc import chooser
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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from migen.genlib.record import Record
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from migen.flow.actor import Sink, Source
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class UARTRX(Module):
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def __init__(self, pads, tuning_word):
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self.source = Source([("d", 8)])
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###
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uart_clk_rxen = Signal()
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phase_accumulator_rx = Signal(32)
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rx = Signal()
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self.specials += MultiReg(pads.rx, rx)
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rx_r = Signal()
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rx_reg = Signal(8)
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rx_bitcount = Signal(4)
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rx_busy = Signal()
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rx_done = self.source.stb
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rx_data = self.source.d
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self.sync += [
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rx_done.eq(0),
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rx_r.eq(rx),
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If(~rx_busy,
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If(~rx & rx_r, # look for start bit
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rx_busy.eq(1),
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rx_bitcount.eq(0),
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)
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).Else(
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If(uart_clk_rxen,
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rx_bitcount.eq(rx_bitcount + 1),
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If(rx_bitcount == 0,
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If(rx, # verify start bit
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rx_busy.eq(0)
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)
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).Elif(rx_bitcount == 9,
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rx_busy.eq(0),
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If(rx, # verify stop bit
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rx_data.eq(rx_reg),
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rx_done.eq(1)
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)
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).Else(
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rx_reg.eq(Cat(rx_reg[1:], rx))
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)
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)
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)
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]
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self.sync += \
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If(rx_busy,
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Cat(phase_accumulator_rx, uart_clk_rxen).eq(phase_accumulator_rx + tuning_word)
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).Else(
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Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31)
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)
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class UARTTX(Module):
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def __init__(self, pads, tuning_word):
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self.sink = Sink([("d", 8)])
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###
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uart_clk_txen = Signal()
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phase_accumulator_tx = Signal(32)
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pads.tx.reset = 1
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tx_reg = Signal(8)
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tx_bitcount = Signal(4)
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tx_busy = Signal()
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self.sync += [
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self.sink.ack.eq(0),
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If(self.sink.stb & ~tx_busy & ~self.sink.ack,
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tx_reg.eq(self.sink.d),
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tx_bitcount.eq(0),
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tx_busy.eq(1),
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pads.tx.eq(0)
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).Elif(uart_clk_txen & tx_busy,
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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pads.tx.eq(1)
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).Elif(tx_bitcount == 9,
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pads.tx.eq(1),
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tx_busy.eq(0),
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self.sink.ack.eq(1),
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).Else(
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pads.tx.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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)
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)
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]
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self.sync += [
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If(tx_busy,
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Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + tuning_word)
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).Else(
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Cat(phase_accumulator_tx, uart_clk_txen).eq(0)
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)
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]
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class UART(Module, AutoCSR):
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def __init__(self, pads, clk_freq, baud=115200):
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self._tuning_word = CSRStorage(32, reset=int((baud/clk_freq)*2**32))
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tuning_word = self._tuning_word.storage
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###
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self.rx = UARTRX(pads, tuning_word)
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self.tx = UARTTX(pads, tuning_word)
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self.submodules += self.rx, self.tx
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class UARTPads:
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def __init__(self):
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self.rx = Signal()
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self.tx = Signal()
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class UARTMux(Module):
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def __init__(self, pads):
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self.sel = Signal(max=2)
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self.shared_pads = UARTPads()
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self.bridge_pads = UARTPads()
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###
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# Route rx pad:
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# when sel==0, route it to shared rx and bridge rx
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# when sel==1, route it only to bridge rx
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self.comb += \
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If(self.sel==0,
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self.shared_pads.rx.eq(pads.rx),
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self.bridge_pads.rx.eq(pads.rx)
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).Else(
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self.bridge_pads.rx.eq(pads.rx)
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)
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# Route tx:
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# when sel==0, route shared tx to pads tx
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# when sel==1, route bridge tx to pads tx
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self.comb += \
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If(self.sel==0,
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pads.tx.eq(self.shared_pads.tx)
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).Else(
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pads.tx.eq(self.bridge_pads.tx)
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)
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class LiteScopeUART2WB(Module, AutoCSR):
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cmds = {
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"write" : 0x01,
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"read" : 0x02
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}
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def __init__(self, pads, clk_freq, baud=115200, share_uart=False):
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self.wishbone = wishbone.Interface()
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if share_uart:
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self._sel = CSRStorage()
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###
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if share_uart:
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uart_mux = UARTMux(pads)
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uart = UART(uart_mux.bridge_pads, clk_freq, baud)
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self.submodules += uart_mux, uart
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self.shared_pads = uart_mux.shared_pads
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self.comb += uart_mux.sel.eq(self._sel.storage)
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else:
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uart = UART(pads, clk_freq, baud)
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self.submodules += uart
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byte_counter = Counter(bits_sign=3)
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word_counter = Counter(bits_sign=8)
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self.submodules += byte_counter, word_counter
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cmd = Signal(8)
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cmd_ce = Signal()
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length = Signal(8)
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length_ce = Signal()
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address = Signal(32)
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address_ce = Signal()
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data = Signal(32)
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rx_data_ce = Signal()
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tx_data_ce = Signal()
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self.sync += [
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If(cmd_ce, cmd.eq(uart.rx.source.d)),
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If(length_ce, length.eq(uart.rx.source.d)),
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If(address_ce, address.eq(Cat(uart.rx.source.d, address[0:24]))),
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If(rx_data_ce,
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data.eq(Cat(uart.rx.source.d, data[0:24]))
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).Elif(tx_data_ce,
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data.eq(self.wishbone.dat_r)
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)
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]
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###
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fsm = InsertReset(FSM(reset_state="IDLE"))
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timeout = Timeout(clk_freq//10)
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self.submodules += fsm, timeout
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self.comb += [
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timeout.ce.eq(1),
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fsm.reset.eq(timeout.reached)
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]
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fsm.act("IDLE",
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timeout.reset.eq(1),
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If(uart.rx.source.stb,
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cmd_ce.eq(1),
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If( (uart.rx.source.d == self.cmds["write"]) |
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(uart.rx.source.d == self.cmds["read"]),
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NextState("RECEIVE_LENGTH")
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),
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byte_counter.reset.eq(1),
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word_counter.reset.eq(1)
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)
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)
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fsm.act("RECEIVE_LENGTH",
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If(uart.rx.source.stb,
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length_ce.eq(1),
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NextState("RECEIVE_ADDRESS")
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)
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)
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fsm.act("RECEIVE_ADDRESS",
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If(uart.rx.source.stb,
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address_ce.eq(1),
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byte_counter.ce.eq(1),
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If(byte_counter.value == 3,
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If(cmd == self.cmds["write"],
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NextState("RECEIVE_DATA")
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).Elif(cmd == self.cmds["read"],
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NextState("READ_DATA")
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),
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byte_counter.reset.eq(1),
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)
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)
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)
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fsm.act("RECEIVE_DATA",
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If(uart.rx.source.stb,
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rx_data_ce.eq(1),
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byte_counter.ce.eq(1),
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If(byte_counter.value == 3,
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NextState("WRITE_DATA"),
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byte_counter.reset.eq(1)
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)
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)
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)
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self.comb += [
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self.wishbone.adr.eq(address + word_counter.value),
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self.wishbone.dat_w.eq(data),
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self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1)
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]
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fsm.act("WRITE_DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(1),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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word_counter.ce.eq(1),
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If(word_counter.value == (length-1),
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NextState("IDLE")
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).Else(
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NextState("RECEIVE_DATA")
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)
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)
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)
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fsm.act("READ_DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(0),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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tx_data_ce.eq(1),
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NextState("SEND_DATA")
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)
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)
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self.comb += \
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chooser(data, byte_counter.value, uart.tx.sink.d, n=4, reverse=True)
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fsm.act("SEND_DATA",
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uart.tx.sink.stb.eq(1),
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If(uart.tx.sink.ack,
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byte_counter.ce.eq(1),
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If(byte_counter.value == 3,
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word_counter.ce.eq(1),
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If(word_counter.value == (length-1),
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NextState("IDLE")
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).Else(
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NextState("READ_DATA"),
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byte_counter.reset.eq(1)
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)
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)
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)
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)
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