Gabriel Somlo b6818c205e cpu/rocket: access PLIC registers via pointer dereference ... Since the PLIC is internal to Rocket, access its registers directly via pointer dereference, rather than through the LiteX CSR Bus accessors (which assume subregister slicing, and are therefore inappropriate for registers NOT accessed over the LiteX CSR Bus). Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>		2019-12-21 12:59:19 -05:00
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cores	cpu/microwatt: add initial software support	2019-12-20 23:32:21 +01:00
integration	cpu/microwatt: add initial software support	2019-12-20 23:32:21 +01:00
interconnect	soc/interconnect/csr: add fields support for CSRStorage's write simulation method	2019-12-02 09:44:44 +01:00
software	cpu/rocket: access PLIC registers via pointer dereference	2019-12-21 12:59:19 -05:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00