43 lines
993 B
Python
43 lines
993 B
Python
from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.flow.actor import Sink, Source
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from misoclib.ethmac.common import *
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class TXLastBE(Module):
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def __init__(self, d_w):
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self.sink = sink = Sink(eth_description(d_w))
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self.source = source = Source(eth_description(d_w))
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###
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ongoing = Signal()
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self.sync += \
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If(self.sink.stb & self.sink.ack,
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If(sink.sop,
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ongoing.eq(1)
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).Elif(sink.last_be,
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ongoing.eq(0)
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)
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)
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self.comb += [
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Record.connect(self.sink, self.source),
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self.source.eop.eq(self.sink.last_be),
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self.source.stb.eq(self.sink.stb & (self.sink.sop | ongoing))
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]
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class RXLastBE(Module):
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def __init__(self, d_w):
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self.sink = sink = Sink(eth_description(d_w))
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self.source = source = Source(eth_description(d_w))
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###
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# TODO/FIXME
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fake = Signal() # to use RenameClockDomain
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self.sync += fake.eq(1)
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self.comb += [
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Record.connect(self.sink, self.source),
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self.source.last_be.eq(self.sink.eop)
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]
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