141 lines
2.6 KiB
Python
141 lines
2.6 KiB
Python
from migen.fhdl.std import *
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from migen.fhdl import verilog
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from migen.bus import csr
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim.icarus import Runner
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from migen.bus.transactions import *
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from miscope.std import cif
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from miscope.std.truthtable import *
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from miscope.storage import *
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from mibuild.tools import write_to_file
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try:
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from csr_header import *
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print("csr_header imported")
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except:
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print("csr_header not found")
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class Csr2Trans():
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def __init__(self):
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self.t = []
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def write_csr(self, adr, value):
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self.t.append(TWrite(adr//4, value))
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def read_csr(self, adr):
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self.t.append(TRead(adr//4))
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return 0
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triggered = False
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dat = 0
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rec_done = False
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dat_rdy = False
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rec_length = 128
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def csr_configure():
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bus = Csr2Trans()
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# Length
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recorder_length_write(bus, rec_length)
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# Offset
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recorder_offset_write(bus, 0)
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# Trigger
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recorder_trigger_write(bus, 1)
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return bus.t
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def csr_read_data():
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bus = Csr2Trans()
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for i in range(rec_length+100):
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recorder_read_dat_read(bus)
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recorder_read_en_write(bus, 1)
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return bus.t
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def csr_transactions():
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for t in csr_configure():
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yield t
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for t in range(100):
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yield None
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global triggered
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triggered = True
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for t in range(512):
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yield None
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for t in csr_read_data():
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yield t
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for t in range(100):
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yield None
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class TB(Module):
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csr_base = 0
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csr_map = {
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"recorder": 1,
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}
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def __init__(self, first_run=False):
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self.csr_base = 0
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# Csr Master
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if not first_run:
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self.submodules.master = csr.Initiator(csr_transactions())
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# Recorder
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self.submodules.recorder = Recorder(32, 1024)
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# Csr
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
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if not first_run:
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self.submodules.csrcon = csr.Interconnect(self.master.bus, self.csrbankarray.get_buses())
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# Recorder Data
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def recorder_data(self, s):
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s.wr(self.recorder.sink.stb, 1)
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if not hasattr(self, "cnt"):
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self.cnt = 0
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self.cnt += 1
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s.wr(self.recorder.sink.payload.d, self.cnt)
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global triggered
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if triggered:
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s.wr(self.recorder.sink.payload.hit, 1)
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triggered = False
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else:
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s.wr(self.recorder.sink.payload.hit, 0)
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# Simulation
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def end_simulation(self, s):
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s.interrupt = self.master.done
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def do_simulation(self, s):
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self.recorder_data(s)
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self.end_simulation(s)
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def main():
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tb = TB(first_run=True)
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csr_py_header = cif.get_py_csr_header(tb.csr_base, tb.csrbankarray)
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write_to_file("csr_header.py", csr_py_header)
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tb = TB()
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sim = Simulator(tb, TopLevel("tb_recorder_csr.vcd"))
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sim.run(2000)
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print("Sim Done")
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input()
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main() |