52 lines
1.4 KiB
Python
52 lines
1.4 KiB
Python
from migen.fhdl.std import *
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"""
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Encoders and decoders between binary and one-hot representation
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i: input (binary or one-hot)
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o: output (one-hot or binary)
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n: "none" signal (in/out), binary value is invalid
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"""
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class Encoder(Module):
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def __init__(self, width):
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self.i = Signal(width) # one-hot
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self.o = Signal(max=width) # binary
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self.n = Signal() # invalid: none or multiple
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act = dict((1<<j, self.o.eq(j)) for j in range(width))
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act["default"] = self.n.eq(1)
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self.comb += Case(self.i, act)
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class PriorityEncoder(Module):
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def __init__(self, width):
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self.i = Signal(width) # one-hot, lsb has priority
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self.o = Signal(max=width) # binary
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self.n = Signal() # none
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for j in range(width)[::-1]: # last has priority
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self.comb += If(self.i[j], self.o.eq(j))
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self.comb += self.n.eq(self.i == 0)
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class Decoder(Module):
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def __init__(self, width):
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self.i = Signal(max=width) # binary
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self.n = Signal() # none/invalid
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self.o = Signal(width) # one-hot
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act = dict((j, self.o.eq(1<<j)) for j in range(width))
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self.comb += Case(self.i, act)
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self.comb += If(self.n, self.o.eq(0))
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class PriorityDecoder(Decoder):
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pass # same
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def _main():
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from migen.fhdl import verilog
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e = Encoder(8)
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print(verilog.convert(e, ios={e.i, e.o, e.n}))
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pe = PriorityEncoder(8)
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print(verilog.convert(pe, ios={pe.i, pe.o, pe.n}))
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d = Decoder(8)
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print(verilog.convert(d, ios={d.i, d.n, d.o}))
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if __name__ == "__main__":
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_main()
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