212 lines
6.1 KiB
Python
212 lines
6.1 KiB
Python
import os, atexit
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from migen.bank import csrgen
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from migen.bus import wishbone, csr
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from migen.bus import wishbone2csr
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from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.bank.description import *
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from misoclib import identifier
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from litescope.common import *
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from litescope.bridge.uart2wb import LiteScopeUART2WB
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from litescope.frontend.la import LiteScopeLA
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from litescope.core.port import LiteScopeTerm
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from liteeth.common import *
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from liteeth.phy.gmii import LiteEthPHYGMII
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from liteeth.core import LiteEthUDPIPCore
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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self.reset = Signal()
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 166MHz
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p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
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p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
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p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset),
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]
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class GenSoC(Module):
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csr_base = 0x00000000
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csr_data_width = 32
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csr_map = {
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"bridge": 0,
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"identifier": 1,
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}
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interrupt_map = {}
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cpu_type = None
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def __init__(self, platform, clk_freq):
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self.clk_freq = clk_freq
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# UART <--> Wishbone bridge
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self.submodules.bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baud=921600)
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# CSR bridge 0x00000000 (shadow @0x00000000)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(self.csr_data_width))
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self._wb_masters = [self.bridge.wishbone]
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self._wb_slaves = [(lambda a: a[23:25] == 0, self.wishbone2csr.wishbone)]
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self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
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# CSR
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self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
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def add_cpu_memory_region(self, name, origin, length):
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self.cpu_memory_regions.append((name, origin, length))
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def add_cpu_csr_region(self, name, origin, busword, obj):
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self.cpu_csr_regions.append((name, origin, busword, obj))
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def do_finalize(self):
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width)
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
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class UDPIPBISTGeneratorUnit(Module):
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def __init__(self):
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self.start = Signal()
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self.src_port = Signal(16)
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self.dst_port = Signal(16)
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self.ip_address = Signal(32)
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self.length = Signal(16)
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self.done = Signal()
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self.source = source = Source(eth_udp_user_description(8))
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###
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counter = Counter(bits_sign=16)
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self.submodules += counter
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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self.done.eq(1),
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counter.reset.eq(1),
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If(self.start,
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NextState("SEND")
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)
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)
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self.comb += [
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source.sop.eq(counter.value == 0),
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source.eop.eq(counter.value == (self.length-1)),
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source.src_port.eq(self.src_port),
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source.dst_port.eq(self.dst_port),
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source.ip_address.eq(self.ip_address),
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source.data.eq(counter.value)
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]
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fsm.act("SEND",
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source.stb.eq(1),
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If(source.stb & source.ack,
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counter.ce.eq(1),
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If(source.eop,
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NextState("IDLE")
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)
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)
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)
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class UDPIPBISTGenerator(UDPIPBISTGeneratorUnit, AutoCSR):
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def __init__(self):
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self._start = CSR()
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self._src_port = CSRStorage(16)
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self._dst_port = CSRStorage(16)
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self._ip_address = CSRStorage(32)
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self._length = CSRStorage(16)
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self._done = CSRStatus()
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###
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UDPIPBISTGeneratorUnit.__init__(self)
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self.comb += [
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self.start.eq(self._start.r & self._start.re),
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self.src_port.eq(self._src_port.storage),
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self.dst_port.eq(self._dst_port.storage),
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self.ip_address.eq(self._ip_address.storage),
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self.length.eq(self._length.storage),
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self._done.status.eq(self.done)
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]
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class UDPIPSoC(GenSoC, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"ethphy": 11,
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"udpipcore": 12,
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"bist_generator": 13
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}
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csr_map.update(GenSoC.csr_map)
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def __init__(self, platform):
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clk_freq = 166*1000000
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GenSoC.__init__(self, platform, clk_freq)
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self.submodules.crg = _CRG(platform)
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# Ethernet PHY and UDP/IP
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self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
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self.submodules.udpipcore = LiteEthUDPIPCore(self.ethphy, 0x12345678, 0x10e2d5000000)
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# BIST
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self.submodules.bist_generator = UDPIPBISTGenerator()
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self.comb += [
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Record.connect(self.bist_generator.source, self.udpipcore.sink),
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self.udpipcore.source.ack.eq(1)
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]
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class UDPIPSoCDevel(UDPIPSoC, AutoCSR):
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csr_map = {
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"la": 20
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}
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csr_map.update(UDPIPSoC.csr_map)
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def __init__(self, platform):
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UDPIPSoC.__init__(self, platform)
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debug = (
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Signal(),
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Signal()
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)
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self.submodules.la = LiteScopeLA(debug, 2048)
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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atexit.register(self.exit, platform)
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def do_finalize(self):
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UDPIPSoC.do_finalize(self)
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def exit(self, platform):
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if platform.vns is not None:
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self.la.export(platform.vns, "../test/la.csv")
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default_subtarget = UDPIPSoC
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