114 lines
2.8 KiB
Python
114 lines
2.8 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory
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from migen.fhdl.module import Module
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from migen.genlib.cdc import MultiReg, GrayCounter
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def _inc(signal, modulo):
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if modulo == 2**len(signal):
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return signal.eq(signal + 1)
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else:
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return If(signal == (modulo - 1),
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signal.eq(0)
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).Else(
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signal.eq(signal + 1)
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)
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class _FIFOInterface:
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def __init__(self, width, depth):
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self.din = Signal(width)
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self.we = Signal()
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self.writable = Signal() # not full
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self.dout = Signal(width)
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self.re = Signal()
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self.readable = Signal() # not empty
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class SyncFIFO(Module, _FIFOInterface):
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def __init__(self, width, depth):
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_FIFOInterface.__init__(self, width, depth)
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###
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do_write = Signal()
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do_read = Signal()
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self.comb += [
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do_write.eq(self.writable & self.we),
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do_read.eq(self.readable & self.re)
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]
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level = Signal(max=depth+1)
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produce = Signal(max=depth)
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consume = Signal(max=depth)
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storage = Memory(width, depth)
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self.specials += storage
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wrport = storage.get_port(write_capable=True)
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self.comb += [
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wrport.adr.eq(produce),
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wrport.dat_w.eq(self.din),
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wrport.we.eq(do_write)
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]
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self.sync += If(do_write, _inc(produce, depth))
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rdport = storage.get_port(async_read=True)
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self.comb += [
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rdport.adr.eq(consume),
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self.dout.eq(rdport.dat_r)
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]
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self.sync += If(do_read, _inc(consume, depth))
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self.sync += [
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If(do_write,
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If(~do_read, level.eq(level + 1))
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).Elif(do_read,
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level.eq(level - 1)
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)
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]
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self.comb += [
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self.writable.eq(level != depth),
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self.readable.eq(level != 0)
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]
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class AsyncFIFO(Module, _FIFOInterface):
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def __init__(self, width, depth):
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_FIFOInterface.__init__(self, width, depth)
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###
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depth_bits = log2_int(depth, True)
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produce = GrayCounter(depth_bits+1)
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self.add_submodule(produce, "write")
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consume = GrayCounter(depth_bits+1)
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self.add_submodule(consume, "read")
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self.comb += [
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produce.ce.eq(self.writable & self.we),
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consume.ce.eq(self.readable & self.re)
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]
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# TODO: disable retiming on produce.q and consume.q
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produce_rdomain = Signal(depth_bits+1)
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self.specials += MultiReg(produce.q, produce_rdomain, "read")
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consume_wdomain = Signal(depth_bits+1)
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self.specials += MultiReg(consume.q, consume_wdomain, "write")
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self.comb += [
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self.writable.eq((produce.q[-1] == consume_wdomain[-1])
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| (produce.q[-2] == consume_wdomain[-2])
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| (produce.q[:-2] != consume_wdomain[:-2])),
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self.readable.eq(consume.q != produce_rdomain)
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]
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storage = Memory(width, depth)
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self.specials += storage
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wrport = storage.get_port(write_capable=True, clock_domain="write")
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self.comb += [
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wrport.adr.eq(produce.q_binary[:-1]),
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wrport.dat_w.eq(self.din),
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wrport.we.eq(produce.ce)
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]
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rdport = storage.get_port(clock_domain="read")
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self.comb += [
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rdport.adr.eq(consume.q_binary[:-1]),
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self.dout.eq(rdport.dat_r)
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]
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