Florent Kermarrec 9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code ... it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.		2015-03-17 00:40:26 +01:00
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__init__.py
bitcontainer.py
decorators.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00
edif.py
module.py
namer.py
simplify.py
specials.py
std.py
structure.py
tools.py
tracer.py
verilog.py
visit.py