135 lines
4.0 KiB
Python
135 lines
4.0 KiB
Python
import os
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from fractions import Fraction
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from migen.fhdl.std import *
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from mibuild.generic_platform import ConstraintError
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from misoclib import sdram, mxcrg, norflash16, minimac3, framebuffer, gpio
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from misoclib.sdram.phy import s6ddrphy
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from misoclib.gensoc import SDRAMSoC
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from misoclib.ethmac.phy import mii
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class _MXClockPads:
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def __init__(self, platform):
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self.clk50 = platform.request("clk50")
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self.trigger_reset = 0
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try:
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self.trigger_reset = platform.request("user_btn", 1)
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except ConstraintError:
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pass
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self.norflash_rst_n = platform.request("norflash_rst_n")
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ddram_clock = platform.request("ddram_clock")
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self.ddr_clk_p = ddram_clock.p
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self.ddr_clk_n = ddram_clock.n
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class BaseSoC(SDRAMSoC):
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default_platform = "mixxeo" # also supports m1
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def __init__(self, platform, **kwargs):
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SDRAMSoC.__init__(self, platform,
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clk_freq=(83 + Fraction(1, 3))*1000000,
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cpu_reset_address=0x00180000,
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**kwargs)
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sdram_geom = sdram.GeomSettings(
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bank_a=2,
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row_a=13,
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col_a=10
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)
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sdram_timing = sdram.TimingSettings(
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tRP=self.ns(15),
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tRCD=self.ns(15),
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tWR=self.ns(15),
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tWTR=2,
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tREFI=self.ns(7800, False),
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tRFC=self.ns(70),
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req_queue_size=8,
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read_time=32,
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write_time=16
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)
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
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rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
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self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
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self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
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self.ns(110), self.ns(50))
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self.flash_boot_address = 0x001a0000
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self.register_rom(self.norflash.bus)
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self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
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self.comb += [
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
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]
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platform.add_platform_command("""
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INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
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INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
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PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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platform.add_source_dir(os.path.join("verilog", "mxcrg"))
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class MiniSoC(BaseSoC):
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csr_map = {
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"ethphy": 10,
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"ethmac": 11,
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}
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csr_map.update(BaseSoC.csr_map)
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interrupt_map = {
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"ethmac": 2,
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}
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interrupt_map.update(BaseSoC.interrupt_map)
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def __init__(self, platform, **kwargs):
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BaseSoC.__init__(self, platform, **kwargs)
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if platform.name == "mixxeo":
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self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
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if platform.name == "m1":
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self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0), platform.request("user_btn", 2)))
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self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2)))
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self.submodules.ethphy = mii.MIIPHY(platform.request("eth_clocks"), platform.request("eth"))
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self.submodules.ethmac = ethmac.EthMAC(phy=self.ethphy, with_hw_preamble_crc=False)
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self.add_wb_slave(lambda a: a[26:29] == 3, self.ethmac.bus)
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self.add_cpu_memory_region("ethmac_mem", 0xb0000000, 0x2000)
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def get_vga_dvi(platform):
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try:
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pads_vga = platform.request("vga_out")
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except ConstraintError:
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pads_vga = None
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try:
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pads_dvi = platform.request("dvi_out")
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except ConstraintError:
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pads_dvi = None
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else:
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platform.add_platform_command("""
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PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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return pads_vga, pads_dvi
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def add_vga_tig(platform, fb):
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platform.add_platform_command("""
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NET "{vga_clk}" TNM_NET = "GRPvga_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
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""", vga_clk=fb.driver.clocking.cd_pix.clk)
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class FramebufferSoC(MiniSoC):
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csr_map = {
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"fb": 11,
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}
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csr_map.update(MiniSoC.csr_map)
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def __init__(self, platform, **kwargs):
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MiniSoC.__init__(self, platform, **kwargs)
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pads_vga, pads_dvi = get_vga_dvi(platform)
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self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi, self.lasmixbar.get_master())
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add_vga_tig(platform, self.fb)
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default_subtarget = FramebufferSoC
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