366 lines
7.1 KiB
Verilog
366 lines
7.1 KiB
Verilog
/*
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* 1:2 frequency-ratio DDR PHY for Spartan-6
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*
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************* DATAPATH SIGNALS ***********
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* Assert dfi_wrdata_en and present the data
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* on dfi_wrdata_mask/dfi_wrdata in the same
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* cycle as the write command.
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*
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* Assert dfi_rddata_en in the same cycle as the read
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* command. The data will come back on dfi_rddata
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* 4 cycles later, along with the assertion of
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* dfi_rddata_valid.
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*
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* This PHY only supports CAS Latency 3.
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* Read commands must be sent on phase 0.
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* Write commands must be sent on phase 1.
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*/
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module s6ddrphy #(
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parameter NUM_AD = 0,
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parameter NUM_BA = 0,
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parameter NUM_D = 0 /* < number of data lines per DFI phase */
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) (
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/* Clocks */
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input sys_clk,
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input clk2x_270,
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input clk4x_wr,
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input clk4x_wr_strb,
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input clk4x_rd,
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input clk4x_rd_strb,
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/* DFI phase 0 */
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input [NUM_AD-1:0] dfi_address_p0,
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input [NUM_BA-1:0] dfi_bank_p0,
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input dfi_cs_n_p0,
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input dfi_cke_p0,
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input dfi_ras_n_p0,
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input dfi_cas_n_p0,
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input dfi_we_n_p0,
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input dfi_wrdata_en_p0,
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input [NUM_D/8-1:0] dfi_wrdata_mask_p0,
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input [NUM_D-1:0] dfi_wrdata_p0,
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input dfi_rddata_en_p0,
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output [NUM_D-1:0] dfi_rddata_w0,
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output dfi_rddata_valid_w0,
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/* DFI phase 1 */
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input [NUM_AD-1:0] dfi_address_p1,
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input [NUM_BA-1:0] dfi_bank_p1,
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input dfi_cs_n_p1,
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input dfi_cke_p1,
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input dfi_ras_n_p1,
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input dfi_cas_n_p1,
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input dfi_we_n_p1,
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input dfi_wrdata_en_p1,
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input [NUM_D/8-1:0] dfi_wrdata_mask_p1,
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input [NUM_D-1:0] dfi_wrdata_p1,
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input dfi_rddata_en_p1,
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output [NUM_D-1:0] dfi_rddata_w1,
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output dfi_rddata_valid_w1,
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/* DDR SDRAM pads */
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output sd_clk_out_p,
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output sd_clk_out_n,
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output reg [NUM_AD-1:0] sd_a,
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output reg [NUM_BA-1:0] sd_ba,
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output reg sd_cs_n,
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output reg sd_cke,
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output reg sd_ras_n,
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output reg sd_cas_n,
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output reg sd_we_n,
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inout [NUM_D/2-1:0] sd_dq,
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output [NUM_D/16-1:0] sd_dm,
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inout [NUM_D/16-1:0] sd_dqs
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);
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/*
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* SDRAM clock
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*/
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ODDR2 #(
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.DDR_ALIGNMENT("NONE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) sd_clk_forward_p (
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.Q(sd_clk_out_p),
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.C0(clk2x_270),
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.C1(~clk2x_270),
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.CE(1'b1),
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.D0(1'b1),
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.D1(1'b0),
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.R(1'b0),
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.S(1'b0)
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);
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ODDR2 #(
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.DDR_ALIGNMENT("NONE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) sd_clk_forward_n (
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.Q(sd_clk_out_n),
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.C0(clk2x_270),
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.C1(~clk2x_270),
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.CE(1'b1),
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.D0(1'b0),
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.D1(1'b1),
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.R(1'b0),
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.S(1'b0)
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);
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/*
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* Command/address
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*/
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reg phase_sel;
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always @(posedge clk2x_270)
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phase_sel <= sys_clk;
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reg [NUM_AD-1:0] r_dfi_address_p0;
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reg [NUM_BA-1:0] r_dfi_bank_p0;
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reg r_dfi_cs_n_p0;
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reg r_dfi_cke_p0;
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reg r_dfi_ras_n_p0;
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reg r_dfi_cas_n_p0;
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reg r_dfi_we_n_p0;
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reg [NUM_AD-1:0] r_dfi_address_p1;
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reg [NUM_BA-1:0] r_dfi_bank_p1;
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reg r_dfi_cs_n_p1;
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reg r_dfi_cke_p1;
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reg r_dfi_ras_n_p1;
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reg r_dfi_cas_n_p1;
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reg r_dfi_we_n_p1;
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always @(posedge clk2x_270) begin
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r_dfi_address_p0 <= dfi_address_p0;
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r_dfi_bank_p0 <= dfi_bank_p0;
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r_dfi_cs_n_p0 <= dfi_cs_n_p0;
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r_dfi_cke_p0 <= dfi_cke_p0;
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r_dfi_ras_n_p0 <= dfi_ras_n_p0;
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r_dfi_cas_n_p0 <= dfi_cas_n_p0;
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r_dfi_we_n_p0 <= dfi_we_n_p0;
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r_dfi_address_p1 <= dfi_address_p1;
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r_dfi_bank_p1 <= dfi_bank_p1;
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r_dfi_cs_n_p1 <= dfi_cs_n_p1;
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r_dfi_cke_p1 <= dfi_cke_p1;
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r_dfi_ras_n_p1 <= dfi_ras_n_p1;
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r_dfi_cas_n_p1 <= dfi_cas_n_p1;
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r_dfi_we_n_p1 <= dfi_we_n_p1;
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end
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always @(posedge clk2x_270) begin
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if(phase_sel) begin
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sd_a <= r_dfi_address_p0;
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sd_ba <= r_dfi_bank_p0;
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sd_cs_n <= r_dfi_cs_n_p0;
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sd_cke <= r_dfi_cke_p0;
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sd_ras_n <= r_dfi_ras_n_p0;
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sd_cas_n <= r_dfi_cas_n_p0;
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sd_we_n <= r_dfi_we_n_p0;
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end else begin
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sd_a <= r_dfi_address_p1;
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sd_ba <= r_dfi_bank_p1;
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sd_cs_n <= r_dfi_cs_n_p1;
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sd_cke <= r_dfi_cke_p1;
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sd_ras_n <= r_dfi_ras_n_p1;
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sd_cas_n <= r_dfi_cas_n_p1;
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sd_we_n <= r_dfi_we_n_p1;
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end
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end
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/*
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* DQ/DQS/DM data
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*/
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genvar i;
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wire drive_dqs;
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wire [NUM_D/16-1:0] dqs_o;
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wire [NUM_D/16-1:0] dqs_t;
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reg postamble;
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generate
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for(i=0;i<NUM_D/16;i=i+1)
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begin: gen_dqs
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ODDR2 #(
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.DDR_ALIGNMENT("C1"),
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.INIT(1'b0),
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.SRTYPE("ASYNC")
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) dqs_o_oddr (
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.Q(dqs_o[i]),
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.C0(clk2x_270),
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.C1(~clk2x_270),
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.CE(1'b1),
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.D0(1'b0),
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.D1(1'b1),
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.R(1'b0),
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.S(1'b0)
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);
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ODDR2 #(
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.DDR_ALIGNMENT("C1"),
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.INIT(1'b0),
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.SRTYPE("ASYNC")
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) dqs_t_oddr (
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.Q(dqs_t[i]),
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.C0(clk2x_270),
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.C1(~clk2x_270),
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.CE(1'b1),
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.D0(~(drive_dqs | postamble)),
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.D1(~drive_dqs),
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.R(1'b0),
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.S(1'b0)
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);
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OBUFT dqs_obuft(
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.I(dqs_o[i]),
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.T(dqs_t[i]),
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.O(sd_dqs[i])
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);
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end
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endgenerate
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always @(posedge clk2x_270)
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postamble <= drive_dqs;
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wire drive_dq;
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wire [NUM_D/2-1:0] dq_i;
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wire [NUM_D/2-1:0] dq_o;
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wire [NUM_D/2-1:0] dq_t;
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generate
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for(i=0;i<NUM_D/2;i=i+1)
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begin: gen_dq
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OSERDES2 #(
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.DATA_WIDTH(4),
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.DATA_RATE_OQ("SDR"),
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.DATA_RATE_OT("SDR"),
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.SERDES_MODE("NONE"),
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.OUTPUT_MODE("SINGLE_ENDED")
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) dq_oserdes (
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.OQ(dq_o[i]),
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.OCE(1'b1),
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.CLK0(clk4x_wr),
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.CLK1(1'b0),
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.IOCE(clk4x_wr_strb),
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.RST(1'b0),
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.CLKDIV(sys_clk),
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.D1(dfi_wrdata_p0[i+NUM_D/2]),
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.D2(dfi_wrdata_p0[i]),
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.D3(dfi_wrdata_p1[i+NUM_D/2]),
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.D4(dfi_wrdata_p1[i]),
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.TQ(dq_t[i]),
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.T1(~drive_dq),
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.T2(~drive_dq),
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.T3(~drive_dq),
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.T4(~drive_dq),
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.TRAIN(1'b0),
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.TCE(1'b1),
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.SHIFTIN1(1'b0),
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.SHIFTIN2(1'b0),
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.SHIFTIN3(1'b0),
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.SHIFTIN4(1'b0),
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.SHIFTOUT3(),
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.SHIFTOUT4()
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);
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ISERDES2 #(
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.DATA_WIDTH(4),
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.DATA_RATE("SDR"),
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.BITSLIP_ENABLE("FALSE"),
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.SERDES_MODE("NONE"),
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.INTERFACE_TYPE("RETIMED")
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) dq_iserdes (
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.D(dq_i[i]),
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.CE0(1'b1),
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.CLK0(clk4x_rd),
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.CLK1(1'b0),
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.IOCE(clk4x_rd_strb),
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.RST(1'b0),
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.CLKDIV(sys_clk),
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.SHIFTIN(),
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.BITSLIP(1'b0),
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.FABRICOUT(),
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.Q1(dfi_rddata_w0[i+NUM_D/2]),
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.Q2(dfi_rddata_w0[i]),
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.Q3(dfi_rddata_w1[i+NUM_D/2]),
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.Q4(dfi_rddata_w1[i]),
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.DFB(),
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.CFB0(),
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.CFB1(),
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.VALID(),
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.INCDEC(),
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.SHIFTOUT()
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);
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IOBUF dq_iobuf(
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.I(dq_o[i]),
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.O(dq_i[i]),
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.T(dq_t[i]),
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.IO(sd_dq[i])
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);
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end
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endgenerate
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generate
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for(i=0;i<NUM_D/16;i=i+1)
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begin: gen_dm_oserdes
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OSERDES2 #(
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.DATA_WIDTH(4),
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.DATA_RATE_OQ("SDR"),
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.DATA_RATE_OT("SDR"),
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.SERDES_MODE("NONE"),
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.OUTPUT_MODE("SINGLE_ENDED")
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) dm_oserdes (
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.OQ(sd_dm[i]),
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.OCE(1'b1),
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.CLK0(clk4x_wr),
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.CLK1(1'b0),
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.IOCE(clk4x_wr_strb),
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.RST(1'b0),
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.CLKDIV(sys_clk),
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.D1(dfi_wrdata_mask_p0[i+NUM_D/16]),
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.D2(dfi_wrdata_mask_p0[i]),
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.D3(dfi_wrdata_mask_p1[i+NUM_D/16]),
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.D4(dfi_wrdata_mask_p1[i]),
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.TQ(),
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.T1(),
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.T2(),
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.T3(),
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.T4(),
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.TRAIN(1'b0),
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.TCE(1'b0),
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.SHIFTIN1(1'b0),
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.SHIFTIN2(1'b0),
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.SHIFTIN3(1'b0),
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.SHIFTIN4(1'b0),
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.SHIFTOUT1(),
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.SHIFTOUT2(),
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.SHIFTOUT3(),
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.SHIFTOUT4()
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);
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end
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endgenerate
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/*
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* DQ/DQS/DM control
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*/
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reg d_dfi_wrdata_en_p1;
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always @(posedge sys_clk)
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d_dfi_wrdata_en_p1 <= dfi_wrdata_en_p1;
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reg r_dfi_wrdata_en;
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always @(posedge clk2x_270)
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r_dfi_wrdata_en <= d_dfi_wrdata_en_p1;
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reg r2_dfi_wrdata_en;
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always @(posedge clk2x_270)
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r2_dfi_wrdata_en <= r_dfi_wrdata_en;
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assign drive_dqs = r2_dfi_wrdata_en;
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assign drive_dq = d_dfi_wrdata_en_p1;
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wire rddata_valid;
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reg [4:0] rddata_sr;
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assign dfi_rddata_valid_w0 = rddata_sr[0];
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assign dfi_rddata_valid_w1 = rddata_sr[0];
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always @(posedge sys_clk)
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rddata_sr <= {dfi_rddata_en_p0, rddata_sr[4:1]};
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endmodule
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