litex/litex/gen
2017-04-25 15:13:47 +02:00
..
fhdl merge most of misoc 54e1ef82 and migen e93d0601 changes 2017-01-13 03:55:00 +01:00
genlib gen/genlib/cdc: cleanup lcm computation, fix timeout on BusSynchronizer 2017-04-25 15:13:47 +02:00
sim gen/sim/core: do not use reset_less clock_domains for the one that are created (logic may need to access reset signal) 2017-04-25 10:56:19 +02:00
util litex/gen/util/misc: import gcd from math and not fractions (deprecated) 2017-04-24 19:25:24 +02:00
__init__.py merge most of misoc 54e1ef82 and migen e93d0601 changes 2017-01-13 03:55:00 +01:00
MIGEN_LICENSE litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented 2015-11-13 14:44:16 +01:00