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https://github.com/enjoy-digital/litex.git
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litex
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verilog
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Sebastien Bourdeauducq
679d13c99c
another attempt at fixing clock routing issues
2013-05-06 09:56:10 +02:00
..
lm32
lm32: update
2013-02-24 17:42:28 +01:00
m1crg
another attempt at fixing clock routing issues
2013-05-06 09:56:10 +02:00
minimac3
minimac3: move psync
2013-04-25 18:36:45 +02:00
s6ddrphy
Use Mibuild
2013-02-11 18:23:06 +01:00