Florent Kermarrec bc8974dad1 litex_sim: Switch to soc_core_args/soc_core_argdict.		2021-03-24 17:26:48 +01:00
..
build	Compat: Add litex.compat to handle retro-compatibility on API changes and move integration/soc_sdram to it.	2021-03-24 17:21:13 +01:00
compat	compat: Fix (only triggers notice when used) and enable SoCSDRAM compat.	2021-03-24 17:21:26 +01:00
gen	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
soc	integration/soc_core: Move L2/SDRAM arguments soc_core_args.	2021-03-24 17:21:22 +01:00
tools	litex_sim: Switch to soc_core_args/soc_core_argdict.	2021-03-24 17:26:48 +01:00
__init__.py	revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp).	2020-11-05 19:55:18 +01:00