Florent Kermarrec 0f8f89a269 update clock constraints for SATA1 and use sys_clk of 200MHz ... - data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...		2014-12-17 19:24:23 +01:00
..
test.py	update clock constraints for SATA1 and use sys_clk of 200MHz	2014-12-17 19:24:23 +01:00