295 lines
6.6 KiB
Python
295 lines
6.6 KiB
Python
from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.core.link.scrambler import Scrambler
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from migen.fhdl.decorators import ModuleDecorator
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from migen.bank.description import *
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class LiteSATABISTGenerator(Module):
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def __init__(self, user_port):
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self.start = Signal()
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self.sector = Signal(48)
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self.count = Signal(16)
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self.random = Signal()
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self.done = Signal()
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self.aborted = Signal()
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self.errors = Signal(32) # Note: Not used for writes
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###
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source, sink = user_port.sink, user_port.source
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counter = Counter(bits_sign=32)
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self.submodules += counter
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scrambler = scrambler = InsertReset(Scrambler())
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self.submodules += scrambler
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self.comb += [
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scrambler.reset.eq(counter.reset),
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scrambler.ce.eq(counter.ce)
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]
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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self.done.eq(1),
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counter.reset.eq(1),
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If(self.start,
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NextState("SEND_CMD_AND_DATA")
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)
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)
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self.comb += [
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source.sop.eq(counter.value == 0),
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source.eop.eq(counter.value == (logical_sector_size//4*self.count)-1),
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source.write.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(self.count),
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If(self.random,
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source.data.eq(scrambler.value)
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).Else(
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source.data.eq(counter.value)
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)
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]
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fsm.act("SEND_CMD_AND_DATA",
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source.stb.eq(1),
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If(source.stb & source.ack,
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counter.ce.eq(1),
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If(source.eop,
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NextState("WAIT_ACK")
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)
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)
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)
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fsm.act("WAIT_ACK",
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sink.ack.eq(1),
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If(sink.stb,
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NextState("IDLE")
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)
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)
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self.sync += If(sink.stb & sink.ack, self.aborted.eq(sink.failed))
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class LiteSATABISTChecker(Module):
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def __init__(self, user_port):
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self.start = Signal()
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self.sector = Signal(48)
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self.count = Signal(16)
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self.random = Signal()
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self.done = Signal()
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self.aborted = Signal()
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self.errors = Signal(32)
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###
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source, sink = user_port.sink, user_port.source
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counter = Counter(bits_sign=32)
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error_counter = Counter(self.errors, bits_sign=32)
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self.submodules += counter, error_counter
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scrambler = InsertReset(Scrambler())
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self.submodules += scrambler
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self.comb += [
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scrambler.reset.eq(counter.reset),
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scrambler.ce.eq(counter.ce)
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]
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += self.fsm
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fsm.act("IDLE",
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self.done.eq(1),
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counter.reset.eq(1),
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If(self.start,
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error_counter.reset.eq(1),
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NextState("SEND_CMD")
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)
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)
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self.comb += [
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source.sop.eq(1),
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source.eop.eq(1),
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source.read.eq(1),
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source.sector.eq(self.sector),
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source.count.eq(self.count),
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]
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fsm.act("SEND_CMD",
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source.stb.eq(1),
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If(source.ack,
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counter.reset.eq(1),
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NextState("WAIT_ACK")
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)
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)
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fsm.act("WAIT_ACK",
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If(sink.stb & sink.read,
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NextState("RECEIVE_DATA")
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)
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)
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expected_data = Signal(32)
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self.comb += \
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If(self.random,
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expected_data.eq(scrambler.value)
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).Else(
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expected_data.eq(counter.value)
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)
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fsm.act("RECEIVE_DATA",
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sink.ack.eq(1),
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If(sink.stb,
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counter.ce.eq(1),
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If(sink.data != expected_data,
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error_counter.ce.eq(~sink.last)
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),
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If(sink.eop,
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If(sink.last,
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NextState("IDLE")
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).Else(
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NextState("WAIT_ACK")
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)
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)
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)
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)
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self.sync += If(sink.stb & sink.ack, self.aborted.eq(sink.failed))
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class LiteSATABISTUnitCSR(Module, AutoCSR):
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def __init__(self, bist_unit):
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self._start = CSR()
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self._sector = CSRStorage(48)
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self._count = CSRStorage(16)
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self._loops = CSRStorage(8)
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self._random = CSRStorage()
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self._done = CSRStatus()
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self._aborted = CSRStatus()
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self._errors = CSRStatus(32)
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self._cycles = CSRStatus(32)
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###
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self.submodules += bist_unit
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start = self._start.r & self._start.re
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done = self._done.status
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loops = self._loops.storage
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self.comb += [
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bist_unit.sector.eq(self._sector.storage),
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bist_unit.count.eq(self._count.storage),
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bist_unit.random.eq(self._random.storage),
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self._aborted.status.eq(bist_unit.aborted),
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self._errors.status.eq(bist_unit.errors)
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]
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self.fsm = fsm = FSM(reset_state="IDLE")
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loop_counter = Counter(bits_sign=8)
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self.submodules += fsm, loop_counter
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fsm.act("IDLE",
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self._done.status.eq(1),
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loop_counter.reset.eq(1),
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If(start,
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NextState("CHECK")
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)
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)
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fsm.act("CHECK",
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If(loop_counter.value < loops,
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NextState("START")
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).Else(
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NextState("IDLE")
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)
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)
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fsm.act("START",
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bist_unit.start.eq(1),
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NextState("WAIT_DONE")
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)
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fsm.act("WAIT_DONE",
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If(bist_unit.done,
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loop_counter.ce.eq(1),
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NextState("CHECK")
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)
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)
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cycles_counter = Counter(self._cycles.status)
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self.submodules += cycles_counter
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self.sync += [
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cycles_counter.reset.eq(start),
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cycles_counter.ce.eq(~fsm.ongoing("IDLE"))
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]
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class LiteSATABISTIdentify(Module):
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def __init__(self, user_port):
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self.start = Signal()
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self.done = Signal()
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fifo = SyncFIFO([("data", 32)], 512, buffered=True)
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self.submodules += fifo
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self.source = fifo.source
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###
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source, sink = user_port.sink, user_port.source
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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self.done.eq(1),
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If(self.start,
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NextState("SEND_CMD")
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)
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)
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self.comb += [
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source.sop.eq(1),
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source.eop.eq(1),
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source.identify.eq(1),
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]
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fsm.act("SEND_CMD",
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source.stb.eq(1),
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If(source.stb & source.ack,
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NextState("WAIT_ACK")
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)
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)
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fsm.act("WAIT_ACK",
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If(sink.stb & sink.identify,
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NextState("RECEIVE_DATA")
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)
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)
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self.comb += fifo.sink.data.eq(sink.data)
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fsm.act("RECEIVE_DATA",
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sink.ack.eq(fifo.sink.ack),
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If(sink.stb,
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fifo.sink.stb.eq(1),
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If(sink.eop,
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NextState("IDLE")
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)
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)
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)
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class LiteSATABISTIdentifyCSR(Module, AutoCSR):
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def __init__(self, bist_identify):
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self._start = CSR()
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self._done = CSRStatus()
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self._source_stb = CSRStatus()
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self._source_ack = CSR()
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self._source_data = CSRStatus(32)
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###
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self.submodules += bist_identify
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self.comb += [
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bist_identify.start.eq(self._start.r & self._start.re),
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self._done.status.eq(bist_identify.done),
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self._source_stb.status.eq(bist_identify.source.stb),
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self._source_data.status.eq(bist_identify.source.data),
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bist_identify.source.ack.eq(self._source_ack.r & self._source_ack.re)
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]
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class LiteSATABIST(Module, AutoCSR):
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def __init__(self, crossbar, with_csr=False):
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generator = LiteSATABISTGenerator(crossbar.get_port())
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checker = LiteSATABISTChecker(crossbar.get_port())
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identify = LiteSATABISTIdentify(crossbar.get_port())
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if with_csr:
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generator = LiteSATABISTUnitCSR(generator)
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checker = LiteSATABISTUnitCSR(checker)
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identify = LiteSATABISTIdentifyCSR(identify)
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self.submodules.generator = generator
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self.submodules.checker = checker
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self.submodules.identify = identify
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