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litex/migen/bus
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Sebastien Bourdeauducq 04df076fba bank: automatic register naming
2013-03-12 15:45:24 +01:00
..
__init__.py
asmibus.py bus/asmibus: use implicit finalization 2013-03-11 17:11:59 +01:00
csr.py bank: automatic register naming 2013-03-12 15:45:24 +01:00
dfi.py
memory.py
simple.py corelogic -> genlib 2013-02-22 23:19:37 +01:00
transactions.py
wishbone.py corelogic -> genlib 2013-02-22 23:19:37 +01:00
wishbone2asmi.py corelogic -> genlib 2013-02-22 23:19:37 +01:00
wishbone2csr.py corelogic -> genlib 2013-02-22 23:19:37 +01:00