litex/migen
Sebastien Bourdeauducq be68ecfc72 uio: add simulation I/O object 2012-11-17 19:55:33 +01:00
..
actorlib actorlib/sim: swap TokenExchanger parameters 2012-11-17 19:46:28 +01:00
bank bank/description: regprefix 2012-10-15 21:21:59 +02:00
bus bus/csr: allow specifying existing interface 2012-11-17 19:44:25 +01:00
corelogic corelogic/ReorderBuffer: do not touch empty count when issuing and reading at the same time 2012-07-13 20:21:04 +02:00
fhdl fhdl: make constants hashable 2012-11-09 20:17:43 +01:00
flow flow/isd: add freeze register 2012-08-04 23:39:52 +02:00
pytholite uio: unified I/O object 2012-11-17 19:54:50 +01:00
sim Multi-clock design support + new instance API 2012-09-10 23:45:02 +02:00
transform transform/unroll_sync: autodetect in/out 2012-10-15 20:32:07 +02:00
uio uio: add simulation I/O object 2012-11-17 19:55:33 +01:00
__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00