Gabriel Somlo c2938dc973 bios/boot.c: cosmetic: re-indent spisdcardboot() for consistency		2020-03-19 19:37:47 -04:00
..
cores	soc/cores/clock: make sure specific clkoutn_divide_range is only used as a fallback solution.	2020-03-16 11:44:39 +01:00
doc	Add bit more logic to decide when to switch to multilane CSR documentation.	2020-03-13 14:48:56 -07:00
integration	soc/intergration: rename mr_memory_x parameter to memory_x.	2020-03-12 12:20:48 +01:00
interconnect	Fix copyrights	2020-03-05 17:44:10 +01:00
software	bios/boot.c: cosmetic: re-indent spisdcardboot() for consistency	2020-03-19 19:37:47 -04:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00