36 lines
547 B
Verilog
36 lines
547 B
Verilog
module lm32_dp_ram(
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clk_i,
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rst_i,
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we_i,
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waddr_i,
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wdata_i,
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raddr_i,
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rdata_o);
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parameter addr_width = 32;
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parameter addr_depth = 1024;
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parameter data_width = 8;
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input clk_i;
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input rst_i;
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input we_i;
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input [addr_width-1:0] waddr_i;
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input [data_width-1:0] wdata_i;
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input [addr_width-1:0] raddr_i;
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output [data_width-1:0] rdata_o;
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reg [data_width-1:0] ram[addr_depth-1:0];
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reg [addr_width-1:0] raddr_r;
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assign rdata_o = ram[raddr_r];
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always @ (posedge clk_i)
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begin
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if (we_i)
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ram[waddr_i] <= wdata_i;
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raddr_r <= raddr_i;
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end
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endmodule
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