227 lines
6.2 KiB
Python
227 lines
6.2 KiB
Python
from migen.fhdl.structure import *
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from migen.flow.actor import *
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from migen.flow.network import *
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from migen.flow.transactions import *
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from migen.flow import plumbing
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from migen.actorlib import misc, dma_asmi, structuring, sim, spi
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from migen.bank.description import *
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from migen.bank import csrgen
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_hbits = 11
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_vbits = 11
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_bpp = 32
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_bpc = 10
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_pixel_layout = [
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("b", _bpc),
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("g", _bpc),
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("r", _bpc),
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("pad", _bpp-3*_bpc)
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]
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_bpc_dac = 8
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_dac_layout = [
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("hsync", 1),
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("vsync", 1),
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("b", _bpc_dac),
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("g", _bpc_dac),
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("r", _bpc_dac)
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]
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class _FrameInitiator(spi.SingleGenerator):
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def __init__(self, asmi_bits, length_bits, alignment_bits):
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layout = [
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("hres", _hbits, 640),
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("hsync_start", _hbits, 656),
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("hsync_end", _hbits, 752),
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("hscan", _hbits, 799),
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("vres", _vbits, 480),
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("vsync_start", _vbits, 492),
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("vsync_end", _vbits, 494),
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("vscan", _vbits, 524),
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("base", asmi_bits, 0, alignment_bits),
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("length", length_bits, 640*480*4, alignment_bits)
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]
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super().__init__(layout, spi.MODE_CONTINUOUS)
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class VTG(Actor):
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def __init__(self):
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super().__init__(
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("timing", Sink, [
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("hres", _hbits),
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("hsync_start", _hbits),
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("hsync_end", _hbits),
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("hscan", _hbits),
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("vres", _vbits),
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("vsync_start", _vbits),
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("vsync_end", _vbits),
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("vscan", _vbits)]),
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("pixels", Sink, _pixel_layout),
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("dac", Source, _dac_layout)
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)
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def get_fragment(self):
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hactive = Signal()
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vactive = Signal()
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active = Signal()
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generate_en = Signal()
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hcounter = Signal(_hbits)
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vcounter = Signal(_vbits)
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skip = _bpc - _bpc_dac
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comb = [
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active.eq(hactive & vactive),
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If(active,
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self.token("dac").r.eq(self.token("pixels").r[skip:]),
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self.token("dac").g.eq(self.token("pixels").g[skip:]),
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self.token("dac").b.eq(self.token("pixels").b[skip:])
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),
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generate_en.eq(self.endpoints["timing"].stb & (~active | self.endpoints["pixels"].stb)),
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self.endpoints["pixels"].ack.eq(self.endpoints["dac"].ack & active),
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self.endpoints["dac"].stb.eq(generate_en)
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]
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tp = self.token("timing")
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sync = [
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self.endpoints["timing"].ack.eq(0),
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If(generate_en & self.endpoints["dac"].ack,
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hcounter.eq(hcounter + 1),
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If(hcounter == 0, hactive.eq(1)),
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If(hcounter == tp.hres, hactive.eq(0)),
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If(hcounter == tp.hsync_start, self.token("dac").hsync.eq(1)),
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If(hcounter == tp.hsync_end, self.token("dac").hsync.eq(0)),
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If(hcounter == tp.hscan,
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hcounter.eq(0),
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If(vcounter == tp.vscan,
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vcounter.eq(0),
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self.endpoints["timing"].ack.eq(1)
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).Else(
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vcounter.eq(vcounter + 1)
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)
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),
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If(vcounter == 0, vactive.eq(1)),
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If(vcounter == tp.vres, vactive.eq(0)),
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If(vcounter == tp.vsync_start, self.token("dac").vsync.eq(1)),
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If(vcounter == tp.vsync_end, self.token("dac").vsync.eq(0))
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)
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]
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return Fragment(comb, sync)
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class FIFO(Actor):
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def __init__(self):
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super().__init__(("dac", Sink, _dac_layout))
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self.vga_hsync_n = Signal()
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self.vga_vsync_n = Signal()
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self.vga_r = Signal(_bpc_dac)
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self.vga_g = Signal(_bpc_dac)
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self.vga_b = Signal(_bpc_dac)
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def get_fragment(self):
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data_width = 2+3*_bpc_dac
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fifo_full = Signal()
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fifo_write_en = Signal()
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fifo_data_out = Signal(data_width)
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fifo_data_in = Signal(data_width)
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asfifo = Instance("asfifo",
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Instance.Parameter("data_width", data_width),
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Instance.Parameter("address_width", 8),
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Instance.Output("data_out", fifo_data_out),
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Instance.Output("empty"),
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Instance.Input("read_en", 1),
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Instance.ClockPort("clk_read", "vga"),
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Instance.Input("data_in", fifo_data_in),
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Instance.Output("full", fifo_full),
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Instance.Input("write_en", fifo_write_en),
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Instance.ClockPort("clk_write"),
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Instance.Input("rst", 0))
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t = self.token("dac")
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return Fragment(
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[
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Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(asfifo.get_io("data_out")),
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self.endpoints["dac"].ack.eq(~fifo_full),
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fifo_write_en.eq(self.endpoints["dac"].stb),
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fifo_data_in.eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
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self.busy.eq(0)
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],
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instances=[asfifo])
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def sim_fifo_gen():
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while True:
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t = Token("dac")
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yield t
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print("H/V:" + str(t.value["hsync"]) + str(t.value["vsync"])
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+ " " + str(t.value["r"]) + " " + str(t.value["g"]) + " " + str(t.value["b"]))
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class Framebuffer:
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def __init__(self, address, asmiport, simulation=False):
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asmi_bits = asmiport.hub.aw
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alignment_bits = bits_for(asmiport.hub.dw//8) - 1
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length_bits = _hbits + _vbits + 2 - alignment_bits
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pack_factor = asmiport.hub.dw//_bpp
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packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
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fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits)
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adrloop = misc.IntSequence(length_bits, asmi_bits)
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adrbuffer = AbstractActor(plumbing.Buffer)
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dma = dma_asmi.Reader(asmiport)
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datbuffer = AbstractActor(plumbing.Buffer)
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cast = structuring.Cast(asmiport.hub.dw, packed_pixels)
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unpack = structuring.Unpack(pack_factor, _pixel_layout)
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vtg = VTG()
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if simulation:
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fifo = sim.SimActor(sim_fifo_gen(), ("dac", Sink, _dac_layout))
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else:
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fifo = FIFO()
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g = DataFlowGraph()
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g.add_connection(fi, adrloop, source_subr=["length", "base"])
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g.add_connection(adrloop, adrbuffer)
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g.add_connection(adrbuffer, dma)
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g.add_connection(dma, datbuffer)
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g.add_connection(datbuffer, cast)
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g.add_connection(cast, unpack)
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g.add_connection(unpack, vtg, sink_ep="pixels")
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g.add_connection(fi, vtg, sink_ep="timing", source_subr=[
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"hres", "hsync_start", "hsync_end", "hscan",
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"vres", "vsync_start", "vsync_end", "vscan"])
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g.add_connection(vtg, fifo)
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self._comp_actor = CompositeActor(g, debugger=False)
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self.bank = csrgen.Bank(fi.get_registers() + self._comp_actor.get_registers(),
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address=address)
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# Pads
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self.vga_psave_n = Signal()
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if not simulation:
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self.vga_hsync_n = fifo.vga_hsync_n
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self.vga_vsync_n = fifo.vga_vsync_n
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self.vga_sync_n = Signal()
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self.vga_blank_n = Signal()
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if not simulation:
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self.vga_r = fifo.vga_r
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self.vga_g = fifo.vga_g
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self.vga_b = fifo.vga_b
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def get_fragment(self):
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comb = [
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self.vga_sync_n.eq(0),
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self.vga_psave_n.eq(1),
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self.vga_blank_n.eq(1)
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]
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return self.bank.get_fragment() \
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+ self._comp_actor.get_fragment() \
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+ Fragment(comb)
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