Mateusz Holenko c4bb4169f1 soc_core: fix integrated_sram_size argument type ... Right now it's kept as a string and crashes when trying to do math operations on it.		2020-01-23 13:45:16 +01:00
..
cores	cores/clock/xadc: ease DRP timings	2020-01-19 20:57:14 +01:00
integration	soc_core: fix integrated_sram_size argument type	2020-01-23 13:45:16 +01:00
interconnect	soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.	2020-01-16 09:46:54 +01:00
software	bios/sdram: switch to updated CSR accessors, and misc. cleanup	2020-01-13 10:09:02 -05:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00