Florent Kermarrec 275932f56c gen/fhdl/verilog: improve clock domain error reporting.		2020-11-10 13:27:29 +01:00
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fhdl	gen/fhdl/verilog: improve clock domain error reporting.	2020-11-10 13:27:29 +01:00
sim	gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX.	2020-08-23 15:19:46 +02:00
__init__.py	gen: add common with reverse_bits/reverse_bytes functions	2018-10-30 10:15:29 +01:00
common.py	gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX.	2020-08-23 15:19:46 +02:00