Sebastien Bourdeauducq 633e5e6747 fhdl/module/finalize: pass additional args to do_finalize		2013-03-30 11:29:46 +01:00
..
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00
module.py	fhdl/module/finalize: pass additional args to do_finalize	2013-03-30 11:29:46 +01:00
namer.py	New 'specials' API	2013-02-22 17:56:35 +01:00
specials.py	fhdl/specials: clean up clock domain handling	2013-03-26 11:58:34 +01:00
structure.py	Lowering of Special expressions + support ClockSignal/ResetSignal	2013-03-18 18:36:50 +01:00
tools.py	Lowering of Special expressions + support ClockSignal/ResetSignal	2013-03-18 18:36:50 +01:00
tracer.py	bank: automatic register naming	2013-03-12 15:45:24 +01:00
verilog.py	fhdl/specials: clean up clock domain handling	2013-03-26 11:58:34 +01:00
visit.py	Lowering of Special expressions + support ClockSignal/ResetSignal	2013-03-18 18:36:50 +01:00