Jiaxun Yang c52a2ca5df soc/integration/soc: Fix CSRBridge Bus Width conversion ... Wishbone2CSR and AXILite2CSR bridges are incapable for performing bus width conversion, which means it's Bus slave port must have same width as CSRs. Use CSR width to create slave bus to allow width adaptar to be inserted by add_slave. Also add relevant assertion. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>		2024-12-18 10:29:33 +00:00
..
__init__.py
test_avalon_mm.py	Merge branch 'master' into avalon-burst-test	2023-05-10 11:12:30 +02:00
test_axi.py	soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls.	2023-10-27 10:55:13 +02:00
test_axi_lite.py	soc/integration/soc: Fix CSRBridge Bus Width conversion	2024-12-18 10:29:33 +00:00
test_axi_stream.py	test: Add minimal test_axi_stream test (Just syntax check for now).	2022-09-08 11:53:05 +02:00
test_bitbang.py
test_clock.py
test_code_8b10b.py
test_cpu.py	test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated).	2024-05-14 12:53:09 +02:00
test_csr.py	csr_bus: Honour re signal from the upstream bus	2024-06-23 19:35:19 +01:00
test_ecc.py
test_emif.py
test_fifosyncmacro.py	test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow	2022-06-17 16:27:25 +02:00
test_gearbox.py
test_hyperbus.py	soc/cores/hyperbus: Add automatic read burst detection.	2024-08-30 11:53:14 +02:00
test_i2c.py	test_i2c: whitespace cleanups	2024-07-20 15:45:44 +10:00
test_i2s.py
test_icap.py
test_led.py	test/test_led: Comment out TestWS1812 test since seems broken, will need to be investigated/fixed.	2024-10-28 21:51:42 +01:00
test_packet.py
test_prbs.py
test_reduce.py	gen/common/Reduce: Add ADD support.	2022-10-28 19:13:27 +02:00
test_spi.py
test_spi_mmap.py	test/spi_mmap: be less verbose	2024-04-05 12:35:47 +11:00
test_spi_opi.py
test_stream.py	stream/Buffer: Integrate PipeValid/PipeReady (both configurable) and add tests.	2022-09-07 08:59:37 +02:00
test_timer.py
test_wishbone.py	test/test_wishbone: Improve origin_region_remap_test to test more complex remapping.	2024-02-28 19:11:55 +01:00