184 lines
6.1 KiB
Python
184 lines
6.1 KiB
Python
from mibuild.generic_platform import *
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from mibuild.crg import SimpleCRG
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from mibuild.xilinx_common import CRG_DS
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from mibuild.xilinx_ise import XilinxISEPlatform
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from mibuild.xilinx_vivado import XilinxVivadoPlatform
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from mibuild.programmer import XC3SProg
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_io = [
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("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
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("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
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("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
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("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
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("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
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("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
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("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
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("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
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("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
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("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
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("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
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("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
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("clk200", 0,
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Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
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Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
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),
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("clk156", 0,
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Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
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),
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("i2c", 0,
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Subsignal("scl", Pins("K21")),
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Subsignal("sda", Pins("L21")),
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IOStandard("LVCMOS25")),
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("serial", 0,
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Subsignal("cts", Pins("L27")),
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Subsignal("rts", Pins("K23")),
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Subsignal("tx", Pins("K24")),
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Subsignal("rx", Pins("M19")),
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IOStandard("LVCMOS25")),
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("spiflash", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("U19")),
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Subsignal("dq", Pins("P24", "R25", "R20", "R21")),
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IOStandard("LVCMOS25")
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),
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("mmc", 0,
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Subsignal("wp", Pins("Y21")),
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Subsignal("det", Pins("AA21")),
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Subsignal("cmd", Pins("AB22")),
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Subsignal("clk", Pins("AB23")),
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Subsignal("dat", Pins("AC20 AA23 AA22 AC21")),
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IOStandard("LVCMOS25")),
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("lcd", 0,
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Subsignal("db", Pins("AA13 AA10 AA11 Y10")),
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Subsignal("e", Pins("AB10")),
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Subsignal("rs", Pins("Y11")),
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Subsignal("rw", Pins("AB13")),
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IOStandard("LVCMOS15")),
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("rotary", 0,
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Subsignal("a", Pins("Y26")),
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Subsignal("b", Pins("Y25")),
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Subsignal("push", Pins("AA26")),
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IOStandard("LVCMOS25")),
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("hdmi", 0,
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Subsignal("d", Pins("B23 A23 E23 D23 F25 E25 E24 D24 F26 E26 G23 G24 J19 H19 L17 L18 K19 K20")),
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Subsignal("de", Pins("H17")),
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Subsignal("clk", Pins("K18")),
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Subsignal("vsync", Pins("H20")),
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Subsignal("hsync", Pins("J18")),
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Subsignal("int", Pins("AH24")),
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Subsignal("spdif", Pins("J17")),
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Subsignal("spdif_out", Pins("G20")),
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IOStandard("LVCMOS25")),
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("ddram", 0,
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Subsignal("a", Pins(
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"AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14",
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"AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
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Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
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IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15",
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"AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18",
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"AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19",
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"AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15",
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"AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6",
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"AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1",
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"AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5",
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"AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"),
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IOStandard("SSTL15_T_DCI")),
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Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"),
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IOStandard("DIFF_SSTL15")),
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Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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Misc("VCCAUX_IO=HIGH")
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("M28")),
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Subsignal("gtx", Pins("K30")),
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Subsignal("rx", Pins("U27")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("L20")),
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Subsignal("int_n", Pins("N30")),
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Subsignal("mdio", Pins("J21")),
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Subsignal("mdc", Pins("R23")),
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Subsignal("dv", Pins("R28")),
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Subsignal("rx_er", Pins("V26")),
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Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")),
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Subsignal("tx_en", Pins("M27")),
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Subsignal("tx_er", Pins("N29")),
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Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")),
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Subsignal("col", Pins("W19")),
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Subsignal("crs", Pins("R30")),
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IOStandard("LVCMOS25")
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),
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]
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def Platform(*args, toolchain="vivado", **kwargs):
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if toolchain == "ise":
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xilinx_platform = XilinxISEPlatform
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elif toolchain == "vivado":
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xilinx_platform = XilinxVivadoPlatform
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else:
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raise ValueError
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class RealPlatform(xilinx_platform):
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bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
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def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
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xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
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def create_programmer(self):
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return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
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def do_finalize(self, fragment):
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try:
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self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
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except ConstraintError:
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pass
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if isinstance(self, XilinxISEPlatform):
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self.add_platform_command("CONFIG DCI_CASCADE = \"33 32 34\";")
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else:
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self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
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return RealPlatform(*args, **kwargs)
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