56 lines
1.6 KiB
Python
56 lines
1.6 KiB
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from misoclib.gensoc import GenSoC, IntegratedBIOS
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_clk1x = Signal()
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self.specials += Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 125MHz
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p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_clk1x,
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p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=270.0, #o_CLKOUT1=,
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
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p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
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p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
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)
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self.specials += Instance("BUFG", i_I=pll_clk1x, o_O=self.cd_sys.clk)
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self.specials += Instance("FD", p_INIT=1, i_D=~pll_locked,
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i_C=self.cd_sys.clk, o_Q=self.cd_sys.rst)
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class BaseSoC(GenSoC, IntegratedBIOS):
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default_platform = "kc705"
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def __init__(self, platform, **kwargs):
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GenSoC.__init__(self, platform,
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clk_freq=125*1000000, cpu_reset_address=0,
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**kwargs)
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IntegratedBIOS.__init__(self)
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self.submodules.crg = _CRG(platform)
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self.submodules.usermem = wishbone.SRAM(64*1024)
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self.add_wb_slave(lambda a: a[27:29] == 2, self.usermem.bus)
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self.add_cpu_memory_region("sdram", 0x40000000, 64*1024)
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default_subtarget = BaseSoC
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