litex/migen/bus
2012-02-13 16:29:38 +01:00
..
__init__.py CSR bus definitions 2011-12-05 00:16:44 +01:00
asmibus.py bus/asmibus: fix typo 2012-02-11 20:56:01 +01:00
csr.py Remove explicit bus names and rely on the new automatic namer 2012-01-27 22:20:57 +01:00
simple.py Remove explicit bus names and rely on the new automatic namer 2012-01-27 22:20:57 +01:00
wishbone.py Remove explicit bus names and rely on the new automatic namer 2012-01-27 22:20:57 +01:00
wishbone2asmi.py bus: Wishbone to ASMI caching bridge (untested) 2012-02-13 16:29:38 +01:00
wishbone2csr.py bus/wishbone2csr: truncate WB data 2012-02-06 18:43:34 +01:00