105 lines
3.3 KiB
Python
105 lines
3.3 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.actorlib import structuring, dma_asmi, spi
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from milkymist.dvisampler.edid import EDID
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from milkymist.dvisampler.clocking import Clocking
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from milkymist.dvisampler.datacapture import DataCapture
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from milkymist.dvisampler.charsync import CharSync
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from milkymist.dvisampler.decoding import Decoding
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from milkymist.dvisampler.chansync import ChanSync
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from milkymist.dvisampler.resdetection import ResolutionDetection
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class DVISampler(Module, AutoCSR):
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def __init__(self, pads):
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self.submodules.edid = EDID(pads)
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self.submodules.clocking = Clocking(pads)
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for datan in range(3):
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name = "data" + str(datan)
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invert = False
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try:
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s = getattr(pads, name)
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except AttributeError:
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s = getattr(pads, name + "_n")
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invert = True
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cap = DataCapture(8, invert)
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setattr(self.submodules, name + "_cap", cap)
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self.comb += [
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cap.pad.eq(s),
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cap.serdesstrobe.eq(self.clocking.serdesstrobe)
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]
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charsync = CharSync()
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setattr(self.submodules, name + "_charsync", charsync)
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self.comb += charsync.raw_data.eq(cap.d)
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decoding = Decoding()
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setattr(self.submodules, name + "_decod", decoding)
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self.comb += [
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decoding.valid_i.eq(charsync.synced),
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decoding.input.eq(charsync.data)
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]
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self.submodules.chansync = ChanSync()
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self.comb += [
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self.chansync.valid_i.eq(self.data0_decod.valid_o & \
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self.data1_decod.valid_o & self.data2_decod.valid_o),
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self.chansync.data_in0.eq(self.data0_decod.output),
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self.chansync.data_in1.eq(self.data1_decod.output),
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self.chansync.data_in2.eq(self.data2_decod.output),
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]
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de = self.chansync.data_out0.de
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r = self.chansync.data_out2.d
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g = self.chansync.data_out1.d
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b = self.chansync.data_out0.d
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hsync = self.chansync.data_out0.c[0]
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vsync = self.chansync.data_out0.c[1]
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self.submodules.resdetection = ResolutionDetection()
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self.comb += [
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self.resdetection.de.eq(de),
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self.resdetection.hsync.eq(hsync),
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self.resdetection.vsync.eq(vsync)
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]
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class RawDVISampler(Module, AutoCSR):
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def __init__(self, pads, asmiport):
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self.submodules.edid = EDID(pads)
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self.submodules.clocking = Clocking(pads)
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invert = False
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try:
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s = getattr(pads, "data0")
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except AttributeError:
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s = getattr(pads, "data0_n")
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invert = True
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self.submodules.data0_cap = DataCapture(8, invert)
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self.comb += [
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self.data0_cap.pad.eq(s),
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self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
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]
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fifo = AsyncFIFO(10, 1024)
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self.add_submodule(fifo, {"write": "pix", "read": "sys"})
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self.comb += [
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fifo.din.eq(self.data0_cap.d),
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fifo.we.eq(1)
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]
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pack_factor = asmiport.hub.dw//16
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self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)], pack_factor)
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self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw)
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self.submodules.dma = spi.DMAWriteController(dma_asmi.Writer(asmiport), spi.MODE_SINGLE_SHOT)
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self.comb += [
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self.packer.sink.stb.eq(fifo.readable),
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fifo.re.eq(self.packer.sink.ack),
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self.packer.sink.payload.word.eq(fifo.dout),
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self.packer.source.connect(self.cast.sink, match_by_position=True),
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self.cast.source.connect(self.dma.data, match_by_position=True)
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]
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