150 lines
4.1 KiB
Python
150 lines
4.1 KiB
Python
from random import Random
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from migen.fhdl.std import *
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from migen.flow.network import *
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from migen.flow.transactions import *
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from migen.actorlib import dma_wishbone, dma_asmi
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from migen.actorlib.sim import *
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from migen.bus import wishbone, asmibus
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from migen.sim.generic import Simulator
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class MyModel:
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def read(self, address):
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return address + 4
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class MyModelWB(MyModel, wishbone.TargetModel):
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def __init__(self):
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self.prng = Random(763627)
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def can_ack(self, bus):
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return self.prng.randrange(0, 2)
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class MyModelASMI(MyModel, asmibus.TargetModel):
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pass
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def adrgen_gen():
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for i in range(10):
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print("Address: " + hex(i))
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yield Token("address", {"a": i})
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class SimAdrGen(SimActor):
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def __init__(self, nbits):
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self.address = Source([("a", nbits)])
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SimActor.__init__(self, adrgen_gen())
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def dumper_gen():
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while True:
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t = Token("data", idle_wait=True)
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yield t
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print("Received: " + hex(t.value["d"]))
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class SimDumper(SimActor):
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def __init__(self):
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self.data = Sink([("d", 32)])
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SimActor.__init__(self, dumper_gen())
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def trgen_gen():
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for i in range(10):
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a = i
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d = i+10
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print("Address: " + hex(a) + " Data: " + hex(d))
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yield Token("address_data", {"a": a, "d": d})
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class SimTrGen(SimActor):
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def __init__(self, a_nbits):
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self.address_data = Source([("a", a_nbits), ("d", 32)])
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SimActor.__init__(self, trgen_gen())
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class TBWishbone(Module):
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def __init__(self, master):
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self.submodules.peripheral = wishbone.Target(MyModelWB())
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self.submodules.tap = wishbone.Tap(self.peripheral.bus)
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self.submodules.interconnect = wishbone.InterconnectPointToPoint(master.bus,
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self.peripheral.bus)
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class TBWishboneReader(TBWishbone):
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def __init__(self):
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self.adrgen = SimAdrGen(30)
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self.reader = dma_wishbone.Reader()
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self.dumper = SimDumper()
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g = DataFlowGraph()
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g.add_connection(self.adrgen, self.reader)
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g.add_connection(self.reader, self.dumper)
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self.submodules.comp = CompositeActor(g)
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TBWishbone.__init__(self, self.reader)
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def do_simulation(self, s):
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s.interrupt = self.adrgen.token_exchanger.done and not s.rd(self.comp.busy)
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class TBWishboneWriter(TBWishbone):
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def __init__(self):
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self.trgen = SimTrGen(30)
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self.writer = dma_wishbone.Writer()
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g = DataFlowGraph()
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g.add_connection(self.trgen, self.writer)
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self.submodules.comp = CompositeActor(g)
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TBWishbone.__init__(self, self.writer)
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def do_simulation(self, s):
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s.interrupt = self.trgen.token_exchanger.done and not s.rd(self.comp.busy)
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class TBAsmi(Module):
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def __init__(self, nslots):
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self.submodules.hub = asmibus.Hub(32, 32)
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self.port = self.hub.get_port(nslots)
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self.hub.finalize()
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self.submodules.peripheral = asmibus.Target(MyModelASMI(), self.hub)
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self.submodules.tap = asmibus.Tap(self.hub)
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class TBAsmiReader(TBAsmi):
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def __init__(self, nslots):
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TBAsmi.__init__(self, nslots)
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self.adrgen = SimAdrGen(32)
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self.reader = dma_asmi.Reader(self.port)
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self.dumper = SimDumper()
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g = DataFlowGraph()
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g.add_connection(self.adrgen, self.reader)
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g.add_connection(self.reader, self.dumper)
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self.submodules.comp = CompositeActor(g)
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def do_simulation(self, s):
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s.interrupt = self.adrgen.token_exchanger.done and not s.rd(self.comp.busy)
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class TBAsmiWriter(TBAsmi):
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def __init__(self, nslots):
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TBAsmi.__init__(self, nslots)
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self.trgen = SimTrGen(32)
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self.writer = dma_asmi.Writer(self.port)
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g = DataFlowGraph()
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g.add_connection(self.trgen, self.writer)
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self.submodules.comp = CompositeActor(g)
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def do_simulation(self, s):
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s.interrupt = self.trgen.token_exchanger.done and not s.rd(self.comp.busy)
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def test_wb_reader():
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print("*** Testing Wishbone reader")
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Simulator(TBWishboneReader()).run()
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def test_wb_writer():
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print("*** Testing Wishbone writer")
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Simulator(TBWishboneWriter()).run()
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def test_asmi_reader(nslots):
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print("*** Testing ASMI reader (nslots={})".format(nslots))
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Simulator(TBAsmiReader(nslots)).run()
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def test_asmi_writer(nslots):
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print("*** Testing ASMI writer (nslots={})".format(nslots))
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Simulator(TBAsmiWriter(nslots)).run()
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test_wb_reader()
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test_wb_writer()
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test_asmi_reader(1)
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test_asmi_reader(2)
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test_asmi_writer(1)
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test_asmi_writer(2)
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