226 lines
7.1 KiB
Python
226 lines
7.1 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.roundrobin import *
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from migen.genlib.misc import optree
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from migen.genlib.fsm import FSM
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class CommandRequest:
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def __init__(self, a, ba):
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self.a = Signal(a)
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self.ba = Signal(ba)
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self.cas_n = Signal(reset=1)
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self.ras_n = Signal(reset=1)
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self.we_n = Signal(reset=1)
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class CommandRequestRW(CommandRequest):
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def __init__(self, a, ba, tagbits):
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CommandRequest.__init__(self, a, ba)
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self.stb = Signal()
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self.ack = Signal()
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self.is_read = Signal()
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self.is_write = Signal()
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self.tag = Signal(tagbits)
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class _CommandChooser(Module):
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def __init__(self, requests, tagbits):
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self.want_reads = Signal()
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self.want_writes = Signal()
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# NB: cas_n/ras_n/we_n are 1 when stb is inactive
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self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba), tagbits)
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###
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rr = RoundRobin(len(requests), SP_CE)
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self.submodules += rr
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self.comb += [rr.request[i].eq(req.stb & ((req.is_read == self.want_reads) | (req.is_write == self.want_writes)))
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for i, req in enumerate(requests)]
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stb = Signal()
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self.comb += stb.eq(Array(req.stb for req in requests)[rr.grant])
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for name in ["a", "ba", "is_read", "is_write", "tag"]:
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choices = Array(getattr(req, name) for req in requests)
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self.comb += getattr(self.cmd, name).eq(choices[rr.grant])
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for name in ["cas_n", "ras_n", "we_n"]:
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# we should only assert those signals when stb is 1
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choices = Array(getattr(req, name) for req in requests)
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self.comb += If(self.cmd.stb, getattr(self.cmd, name).eq(choices[rr.grant]))
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self.comb += self.cmd.stb.eq(stb \
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& (self.cmd.is_read == self.want_reads) \
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& (self.cmd.is_write == self.want_writes))
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self.comb += [If(self.cmd.stb & self.cmd.ack & (rr.grant == i), req.ack.eq(1))
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for i, req in enumerate(requests)]
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self.comb += rr.ce.eq(self.cmd.ack)
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class _Steerer(Module):
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def __init__(self, commands, dfi):
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ncmd = len(commands)
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nph = len(dfi.phases)
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self.sel = [Signal(max=ncmd) for i in range(nph)]
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###
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def stb_and(cmd, attr):
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if not hasattr(cmd, "stb"):
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return 0
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else:
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return cmd.stb & getattr(cmd, attr)
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for phase, sel in zip(dfi.phases, self.sel):
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self.comb += [
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phase.cke.eq(1),
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phase.cs_n.eq(0)
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]
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self.sync += [
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phase.address.eq(Array(cmd.a for cmd in commands)[sel]),
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phase.bank.eq(Array(cmd.ba for cmd in commands)[sel]),
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phase.cas_n.eq(Array(cmd.cas_n for cmd in commands)[sel]),
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phase.ras_n.eq(Array(cmd.ras_n for cmd in commands)[sel]),
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phase.we_n.eq(Array(cmd.we_n for cmd in commands)[sel]),
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phase.rddata_en.eq(Array(stb_and(cmd, "is_read") for cmd in commands)[sel]),
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phase.wrdata_en.eq(Array(stb_and(cmd, "is_write") for cmd in commands)[sel])
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]
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class _Datapath(Module):
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def __init__(self, timing_settings, command, dfi, hub):
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tagbits = flen(hub.tag_call)
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rd_valid = Signal()
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rd_tag = Signal(tagbits)
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wr_valid = Signal()
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wr_tag = Signal(tagbits)
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self.comb += [
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hub.call.eq(rd_valid | wr_valid),
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If(wr_valid,
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hub.tag_call.eq(wr_tag)
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).Else(
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hub.tag_call.eq(rd_tag)
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)
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]
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rd_delay = timing_settings.rd_delay + 1
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rd_valid_d = [Signal() for i in range(rd_delay)]
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rd_tag_d = [Signal(tagbits) for i in range(rd_delay)]
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for i in range(rd_delay):
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if i:
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self.sync += [
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rd_valid_d[i].eq(rd_valid_d[i-1]),
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rd_tag_d[i].eq(rd_tag_d[i-1])
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]
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else:
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self.sync += [
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rd_valid_d[i].eq(command.stb & command.ack & command.is_read),
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rd_tag_d[i].eq(command.tag)
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]
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self.comb += [
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rd_valid.eq(rd_valid_d[-1]),
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rd_tag.eq(rd_tag_d[-1]),
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wr_valid.eq(command.stb & command.ack & command.is_write),
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wr_tag.eq(command.tag),
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]
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all_rddata = [p.rddata for p in dfi.phases]
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all_wrdata = [p.wrdata for p in dfi.phases]
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all_wrdata_mask = [p.wrdata_mask for p in dfi.phases]
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self.comb += [
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hub.dat_r.eq(Cat(*all_rddata)),
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Cat(*all_wrdata).eq(hub.dat_w),
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Cat(*all_wrdata_mask).eq(hub.dat_wm)
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]
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class Multiplexer(Module):
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def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, hub):
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assert(phy_settings.nphases == len(dfi.phases))
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if phy_settings.nphases != 2:
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raise NotImplementedError("TODO: multiplexer only supports 2 phases")
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# Command choosing
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requests = [bm.cmd for bm in bank_machines]
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tagbits = flen(hub.tag_call)
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choose_cmd = _CommandChooser(requests, tagbits)
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choose_req = _CommandChooser(requests, tagbits)
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self.comb += [
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choose_cmd.want_reads.eq(0),
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choose_cmd.want_writes.eq(0)
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]
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self.submodules += choose_cmd, choose_req
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# Command steering
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nop = CommandRequest(geom_settings.mux_a, geom_settings.bank_a)
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commands = [nop, choose_cmd.cmd, choose_req.cmd, refresher.cmd] # nop must be 1st
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(STEER_NOP, STEER_CMD, STEER_REQ, STEER_REFRESH) = range(4)
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steerer = _Steerer(commands, dfi)
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self.submodules += steerer
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# Read/write turnaround
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read_available = Signal()
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write_available = Signal()
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self.comb += [
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read_available.eq(optree("|", [req.stb & req.is_read for req in requests])),
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write_available.eq(optree("|", [req.stb & req.is_write for req in requests]))
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]
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def anti_starvation(timeout):
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en = Signal()
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max_time = Signal()
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if timeout:
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t = timeout - 1
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time = Signal(max=t+1)
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self.comb += max_time.eq(time == 0)
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self.sync += If(~en,
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time.eq(t)
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).Elif(~max_time,
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time.eq(time - 1)
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)
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else:
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self.comb += max_time.eq(0)
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return en, max_time
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read_time_en, max_read_time = anti_starvation(timing_settings.read_time)
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write_time_en, max_write_time = anti_starvation(timing_settings.write_time)
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# Refresh
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self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines]
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go_to_refresh = Signal()
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self.comb += go_to_refresh.eq(optree("&", [bm.refresh_gnt for bm in bank_machines]))
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# Datapath
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datapath = _Datapath(timing_settings, choose_req.cmd, dfi, hub)
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self.submodules += datapath
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# Control FSM
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fsm = FSM("READ", "WRITE", "REFRESH", delayed_enters=[
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("RTW", "WRITE", timing_settings.rd_delay),
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("WTR", "READ", timing_settings.tWR)
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])
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self.submodules += fsm
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fsm.act(fsm.READ,
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read_time_en.eq(1),
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choose_req.want_reads.eq(1),
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choose_cmd.cmd.ack.eq(1),
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choose_req.cmd.ack.eq(1),
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steerer.sel[1-phy_settings.rdphase].eq(STEER_CMD),
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steerer.sel[phy_settings.rdphase].eq(STEER_REQ),
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If(write_available,
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# TODO: switch only after several cycles of ~read_available?
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If(~read_available | max_read_time, fsm.next_state(fsm.RTW))
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),
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If(go_to_refresh, fsm.next_state(fsm.REFRESH))
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)
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fsm.act(fsm.WRITE,
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write_time_en.eq(1),
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choose_req.want_writes.eq(1),
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choose_cmd.cmd.ack.eq(1),
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choose_req.cmd.ack.eq(1),
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steerer.sel[1-phy_settings.wrphase].eq(STEER_CMD),
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steerer.sel[phy_settings.wrphase].eq(STEER_REQ),
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If(read_available,
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If(~write_available | max_write_time, fsm.next_state(fsm.WTR))
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),
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If(go_to_refresh, fsm.next_state(fsm.REFRESH))
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)
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fsm.act(fsm.REFRESH,
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steerer.sel[0].eq(STEER_REFRESH),
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If(~refresher.req, fsm.next_state(fsm.READ))
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)
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# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
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self.comb += refresher.ack.eq(fsm._state == fsm.REFRESH)
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