Sebastien Bourdeauducq cc6877df9e fhdl: allow use of ResetSignal() on resetless clock domains		2015-07-27 01:51:52 +08:00
..
actorlib	Revert "migen/actorlib/fifo: add FIFO wrapper function"	2015-07-24 19:25:36 +08:00
bank	global: pep8 (E261, E271)	2015-04-13 21:21:30 +02:00
bus	bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant)	2015-06-19 08:37:16 +02:00
fhdl	fhdl: allow use of ResetSignal() on resetless clock domains	2015-07-27 01:51:52 +08:00
flow	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
genlib	migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters)	2015-06-02 19:26:42 +02:00
sim	vpi: cleanup (thanks sb)	2015-05-13 10:13:14 +02:00
test	add examples tests	2015-05-01 00:50:17 +08:00
util	global: pep8 (E302)	2015-04-13 20:45:35 +02:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00